TMPR4956C datasheet(129/286 Pages) TOSHIBA

129 / 286 page

Chapter 8 CPU Exception

8-1

CPU Exception

8.1

Introduction

This chapter describes the explanation of CPU exception processing. The chapter concludes with a

description of each exception’s cause, together with the manner in which the CPU processes and services these

exceptions.

8.2

Exception Vector Locations

Exception vector addresses are stored in an area of kseg0 or kseg1 except for Debug exception vector. The

vector address of the ColdReset, SoftReset and NMI exception is always in a non-cacheable area of kseg1.

Vector addresses of the other exceptions depend on the BEV bit of Status register. When BEV is 0, these

exceptions are vectored to a cacheable area of kseg0. When BEV is 1, all vector addresses are in a

non-cacheable area of kseg1.

Table 8.2.1 shows the list of the exception vector locations.

Table 8.2.1 Exception Vector Locations

Exception

Vector Address (virtual address)

(BEV

= 0)

(BEV

= 1)

ColdReset, SoftReset, NMI

0xffff_ffff_bfc0_0000

TLB refill, EXL

= 0

0xffff_ffff_8000_0000

0xffff_ffff_bfc0_0200

XTLB refill, EXL

= 0

= 64-bit TLB)

0xffff_ffff_8000_0080

0xffff_ffff_bfc0_0280

Others (common exception)

0xffff_ffff_8000_0180

0xffff_ffff_bfc0_0380

Exception

Vector Address (physical address)

(BEV

= 0)

(BEV

= 1)

ColdReset, SoftReset, NMI

0x0_1fc0_0000

TLB refill, EXL

= 0

0x0_0000_0000

0x0_1fc0_0200

XTLB refill, EXL

= 0

= 64-bit TLB)

0x0_0000_0080

0x0_1fc0_0280

Others (common exception)

0x0_0000_0180

0x0_1fc0_0380

The cache error exception is not occurred because the TX4956 does not have the parity bit into the primary

cache. Debug exception needs the care, it has the special address.

Table 8.2.2 shows the list of the debug exception vector locations.

Table 8.2.2 Debug Exception Vector Locations

Exception

Debug Exception Vector Address (virtual address)

(ProbEnb

= 0)

(ProbEnb

= 1)

Debug

0xffff_ffff_bfc0_0400

0xffff_ffff_ff20_0200

Exception

Debug Exception Vector Address (physical address)

(ProbEnb

= 0)

(ProbEnb

= 1)

Debug

0x0_1fc0_0400

0xf_ff20_0200

TMPR4956C Datasheet(PDF) 129 Page - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 129 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL