TMPR4956C datasheet(125/286 Pages) TOSHIBA

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Chapter 6 Write Buffer

6-1

Write Buffer

The processor contains a write buffer to improve the performance of writes to the external memory. Every

write to external memory uses this on-chip write buffer. The write buffer holds up to four 64-bit address and data

pairs.

For a cache miss write-back, the entire buffer is used for the write-back data and allows the processor to

proceed in parallel with the memory update. For uncached and write-through stores, the write buffer uncouples

the CPU from the write to memory. If the write buffer is full, additional stores will stall until there is room for

them in the write buffer.

The processor core might issue a read request while the write buffer is performing a write operation. Multiple

read/write operations are serviced in the following order:

•

If there is only a write request, the data in the write buffer is written to an external device.

•

If there is only a read request, a read operation is performed to bring in data from an external device.

•

If a read request and a write request occur simultaneously, the read request is serviced first, except for

the following cases:

–

when the processor issues a read request to the target address of one of the write buffer entries

–

when the processor issues an uncacheable read reference while the write buffer has uncacheable

write data

The BC0T and BC0F instructions can be used to determine whether any data is present in the write buffer:

•

If there is data in the write buffer, the coprocessor condition signal is false (0).

•

If there is no data in the write buffer, the coprocessor condition signal is true (1).

Following is the assembly language code to freeze the processor until the write buffer becomes empty.

NOP

Loop: BC0F Loop

NOP

The following sequence of instructions also causes the processor to perform the same action. Appended to a

store instruction, the SYNC instruction ensures that the store instruction initiated prior to this instruction is

completed before any instruction after this instruction is allowed to start.

SYNC

TMPR4956C Datasheet(PDF) 125 Page - Toshiba Semiconductor