TMPR4956C datasheet(123/286 Pages) TOSHIBA

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Chapter 5 Cache Organization

5-11

5.10.1

Cache Write Policy

The processor manages its data cache by using a write-back and a write-through policy. A write-back stores

write data into the cache, instead of writing it directly to memory. Some time later this data is

independently written into memory. In the processor implementation, a modified cache line is not written

back to memory until the cache line is to be replaced either in the course of satisfying a cache miss, or

during the execution of a write-back CACHE instruction.

When the processor writes a cache line back to memory, it does not ordinarily retain a copy of the cache

line, and the state of the cache line is changed to invalid.

A write-through is written simultaneously to cache and memory.

Selection of a write policy is done by the K0 bit in the Config register (Reg#16) for the kseg0 segment.

For the other segments, selection of a write policy is done by the C bits in each TLB entry.

5.10.2

Data Cache Line Replacement

Since the data cache uses a write-back and a write-through methodology, a cache line load is issued to

main memory on a load or store miss, as described below. After the data from memory is written to the

data cache, the pipeline resumes execution.

The processor does not support “Critical Data Word First”. Always it transfer the data of first address.

The data cache miss penalties, in number of CPUCLK cycles, are given in Table 5.10.2.

Table 5.10.2 Data Cache Miss Penalty Cycle Count

Number of

CPUCLK Cycles

Action

Stall the DC stage.

Transfer address to the write buffer and wait for the pipeline start signal

1-2

Transfer address to the internal SysAD bus on the GBUSCLK.

Transfer to the external SysAD bus.

Time needed to access memory, measured in CPUCLK cycles.

Transfer the cache line form memory to the SysAD bus.

Transfer the cache line from the external bus to the internal bus.

Restart the DC stage.

TMPR4956C Datasheet(PDF) 123 Page - Toshiba Semiconductor