TMPR4956C datasheet(124/286 Pages) TOSHIBA

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Chapter 5 Cache Organization

5-12

5.10.3

Instruction Cache Line Replacement

For an instruction cache miss, refill is done using sequential ordering, starting from the first word of the

retrieved cache line.

During an instruction cache miss, a memory read is issued. The requested line is returned from memory

and written to the instruction cache. At this time the pipeline resumes execution, and the instruction cache

is reaccessed.

The replacement sequence for an instruction cache miss is:

Move the instruction physical address to the processor pads.

Wait for a CPUCLK cycle, aligned with a GBUSCLK boundary, to occur.

Read the line from memory and write it out to the instruction cache array.

Restart the processor pipe.

The instruction cache miss penalties, in number of CPUCLK, is given in Table 5.10.3.

Table 5.10.3 Instruction Cache Miss Penalty Cycle Count

Number of

CPUCLK

Action

Stall the RF stage.

Transfer address to the write buffer and wait for the pipeline start signal.

1-2

Transfer to the external SysAD bus.

Time needed to access memory, measured in CPUCLK cycles.

Transfer the cache line from memory to the SysAD bus.

Transfer the cache line from the external bus to the internal bus.

Restart the RF stage.

5.11 Manipulation of the Caches by an External Agent

The processor does not provide any mechanisms for an external agent to examine and manipulate the state

and contents of the caches.

TMPR4956C Datasheet(PDF) 124 Page - Toshiba Semiconductor