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TMPR4956C Datasheet(PDF) 119 Page - Toshiba Semiconductor |
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TMPR4956C Datasheet(HTML) 119 Page - Toshiba Semiconductor |
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119 / 286 page  Chapter 5 Cache Organization 5-7 5.4 The Primary Cache Accessing Figure 5.4.1 shows the virtual address (VA) index to the primary cache. Instruction cache size is 32 KB and Data cache size is 32 KB. The virtual address bits be used to index into the primary cache decided by the cache size. Figure 5.4.1 Primary Cache Data and Tag Organization 5.5 Cache States The section describes about the state of a cache line. The cache lines in the processor are in one of states described in Table 5.5.1. The I-Cache line is in one of the following states: • invalid • valid The D-Cache line is in one of the following states: • invalid • valid Table 5.5.1 Cache States Cache Line State Description Invalid A cache line that does not contain valid information must be marked invalid, and cannot be used. A cache line in any other state than invalid is assumed to contain valid information. Valid A cache line contains valid information. The cache line may or not be consistent with memory and is owned by the processor (see “Cache Line Ownership” in this chapter). Tags Tag line Data Data line Instruction Cache: VA[12:5] Data Cache: VA[12:5] Stage WTag VA[12:5] VA[12:5] 64 |
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