TMPR4956C datasheet(116/286 Pages) TOSHIBA

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Chapter 5 Cache Organization

5-4

5.2.6

Organization of the Data Cache (D-Cache)

Each line of D-cache data has an associated 24-bit tag.

The processor D-cache has the following characteristics:

•

Cache size: 32 KB

•

Four-way set associative

•

FIFO replacement

•

Indexed with a virtual address

•

Checked with a physical tag

•

Block (line) size: 8 words (32 bytes)

•

Burst size: 8 words (32 bytes)

•

Store buffer

•

Lockable on a per-line basis (way1 to way3)

•

Write-back or write-through on a per-page basis

•

All Write-back, CS, FIFO and Lock bits are cleared by a Reset exception

5.2.7

Data Cache Address Field

Figure 5.2.5 shows the data cache address field.

Figure 5.2.5 Data Cache Address Field

5.2.8

Data Cache Configuration

Each line in the 4 ways of the data cache share F1, F0 replacement bits. Figure 5.2.6 shows the format

of replacement bits. These bits are shared by way0, way1, way2 and way3 for 32 KB cache, and indicate

next set to which replacement will be directed; when Lock bit is set to 1, indicate this set is not locked.

Each line of data cache data has an associated 28-bit tag that contains a 24-bit physical address, a single

Lock bit, a single Write-back bit and a 2-bit cache state, except for the line in way0, which has an 27-bit

tag that excludes a Lock bit. Figure 5.2.7 shows the formats of tag and data pair.

Figure 5.2.6 Format of Replacement Bits

Cache Tag Index

(8 bits)

Physical Tag

(24 bits )

Word

(2 bits)

Byte

(3 bits)

F0: FIFO replace bit 0

F1: FIFO replace bit 1

TMPR4956C Datasheet(PDF) 116 Page - Toshiba Semiconductor

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