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TMPR4956C Datasheet(PDF) 112 Page - Toshiba Semiconductor |
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TMPR4956C Datasheet(HTML) 112 Page - Toshiba Semiconductor |
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112 / 286 page  Chapter 4 Memory Management System 4-18 TLB Misses If there is no TLB entry that matches the virtual address, a TLB refill exception occurs. (TLB refill exceptions are described in Chapter 8.) If the access control bits (D and V) indicate that the access is not valid, a TLB modification or TLB invalid exception occurs. If the C bits equal 0102, the physical address that is retrieved accesses main memory, bypassing the cache. TLB Instructions Table 4.4.1 lists the instructions that the CPU provides for working with the TLB. See Appendix A for a detailed description of these instructions. Table 4.4.1 TLB Instructions Op Code Description of Instruction TLBP Translation Lookaside Buffer Probe TLBR Translation Lookaside Buffer Read TLBWI Translation Lookaside Buffer Write Index TLBWR Translation Lookaside Buffer Write Random |
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