TMPR4956C datasheet(110/286 Pages) TOSHIBA

110 / 286 page

Chapter 4 Memory Management System

4-16

4.3.3

Instruction-TLB

The processor has a 2-entry instruction TLB (ITLB). Each ITLB entry is a subset of any single JTLB

entry. The ITLB is completely invisible to software.

4.3.4

Data-TLB

The processor has a 4-entry data TLB (DTLB). Each DTLB entry is a subset of any single JTLB entry.

The DTLB is completely invisible to software.

4.4

Virtual-to-Physical Address Translation Process

During virtual-to-physical address translation, the CPU compares the 8-bit ASID (if the Global bit, G, is not

set) of the virtual address to the ASID of the TLB entry to see if there is a match. One of the following

comparisons are also made:

•

In 32-bit mode, the 7 to 19 bits (depending upon the page size) of the virtual address are compared to

the contents of the TLB VPN2 (virtual page number divided by two).

•

In 64-bit mode, the 15 to 27 bits (depending upon the page size) of the virtual address are compared

to the contents of the TLB VPN2 (virtual page number divided by two).

If a TLB entry matches, the physical address and access control bits (C, D, and V) are retrieved from the

matching TLB entry. While the V bit of the entry must be set for a valid translation to take place, it is not

involved in the determination of a matching TLB entry.

Figure 4.4.1 illustrates the TLB address translation process.

TMPR4956C Datasheet(PDF) 110 Page - Toshiba Semiconductor