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TMPR4956C Datasheet(PDF) 106 Page - Toshiba Semiconductor

Part # TMPR4956C
Description  64-Bit TX System RISC TX49 Family
PDF  286 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 106 Page - Toshiba Semiconductor

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Chapter 4 Memory Management System
4-12
Table 4.2.3 32-bit Kernel Mode Segments
Status Register
Is One Of These Values
Address
Bit Values
KSU
EXL
ERL
KX
Segment
Name
Address Range
Segment Size
A[31] = 0
0
Kuseg
0x0000 0000
through
0x7FFF FFFF
2 Gbytes
(2
31 bytes)
A[31:29] = 1002
0
Kseg0
0x8000 0000
through
0x9FFF FFFF
512 Mbytes
(2
29 bytes)
A[31:29] = 1012
0
Kseg1
0xA000 0000
through
0xBFFF FFFF
512 Mbytes
(2
29 bytes)
A[31:29] = 1102
0
Ksseg
0xC000 0000
through
0xDFFF FFFF
512 Mbytes
(2
29 bytes)
Kseg3
0xE000 0000
through
0xFFFF FFFF
512 Mbytes-4 Mbytes
(2
29 bytes)
A[31:29] = 1112
KSU = 002
or
EXL = 1
or
ERL = 1
0
Reserved
(Note)
0xFF00 0000
through
0xFF3F FFFF
4 Mbytes
Note : 0xff00_0000 through 0xff3f_ffff in 32-bit mode is reserved (unmapped, uncached) for use by
registers in the Debug Support Unit and the processor’s peripherals.
32-bit Kernel Mode, User Space (kuseg)
In Kernel mode, when KX
= 0 in the Status register, and the most-significant bit of the virtual address,
A31, is cleared, the 32-bit kuseg virtual address space is selected; it covers the full 2
31 bytes (2 Gbytes) of
the current user address space. The virtual address is extended with the contents of the 8-bit ASID field to
form a unique virtual address. When ERL = 1 in the Status register, the user address region becomes a 2
31
bytes unmapped (that is, mapped directly to physical addresses) uncached address space.
32-bit Kernel Mode, Kernel Space 0 (kseg0)
In Kernel mode, when KX = 0 in the Status register and the most-significant three bits of the virtual
address are 1002, 32-bit kseg0 virtual address space is selected; it is the 2
29 bytes (512 Mbytes) kernel
physical space. References to kseg0 are not mapped through the TLB; the physical address selected is
defined by subtracting 0x8000 0000 from the virtual address. The K0 field of the Config register,
described in this chapter, controls cacheability and coherency.
32-bit Kernel Mode, Kernel Space 1 (kseg1)
In Kernel mode, when KX = 0 in the Status register and the most-significant three bits of the 32-bit
virtual address are 1012, 32-bit kseg1 virtual address space is selected; it is the 2
29 bytes (512 Mbytes)
kernel physical space. References to kseg1 are not mapped through the TLB; the physical address selected
is defined by subtracting 0xA000 0000 from the virtual address. Caches are disabled for accesses to these
addresses, and physical memory (or memory-mapped I/O device registers) are accessed directly.
32-bit Kernel Mode, Supervisor Space (ksseg)
In Kernel mode, when KX = 0 in the Status register and the most-significant three bits of the 32-bit
virtual address are 1102, the ksseg virtual address space is selected; it is the current 2
29 bytes (512 Mbytes)
supervisor virtual space. The virtual address is extended with the contents of the 8-bit ASID field to form
a unique virtual address.



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