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TMPR4956C Datasheet(PDF) 104 Page - Toshiba Semiconductor |
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TMPR4956C Datasheet(HTML) 104 Page - Toshiba Semiconductor |
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104 / 286 page ![]() Chapter 4 Memory Management System 4-10 Figure 4.2.3 Kernel Mode Address Space Note 1: In 32-bit mode, bit 31 is sign-extended through bits 63-32. Failure results in an address error exception. Note 2: 0xff00_0000 through 0xff3f_ffff in 32-bit mode and 0xffff_ffff_ff00_0000 through 0xffff_ffff_ff3f_ffff in 64-bit mode are reserved (unmapped, uncached) for use by registers in the Debug Support Unit and the processor’s peripherals. kuseg kseg0 kseg1 ksseg kseg3 (Note 2) 0x 0000 0000 0x 8000 0000 0x A000 0000 0x C000 0000 0x E000 0000 0x FFFF FFFF 32-bit (Note 1) 2 GB Mapped Cacheable 512 MB Mapped Cacheable 512 MB Mapped Cacheable 512 MB Unmapped Cacheable 512 MB Unmapped Uncached 0x FFFF FFFF E000 0000 0x 0000 0000 0000 0000 0x 0000 0100 0000 0000 0x 4000 0000 0000 0000 0x 4000 0100 0000 0000 0x 8000 0000 0000 0000 0x C000 0000 0000 0000 0x C000 00FF 8000 0000 0x FFFF FFFF 8000 0000 0x FFFF FFFF A000 0000 0x FFFF FFFF C000 0000 0x FFFF FFFF FFFF FFFF xkuseg xksseg xkphys xkseg cksseg ckseg0 ckseg1 ckseg3 (Note 2) 64-bit 512 MB Mapped Cacheable 512 MB Mapped Cacheable 1 TB Mapped Cacheable 1 TB Mapped Cacheable Mapped Cacheable Unmapped (For details see figure 4.2.4) Address error Address error Address error 512 MB Unmapped Uncached 512 MB Unmapped Cacheable |
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