TMPR4956C datasheet(115/286 Pages) TOSHIBA

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Chapter 5 Cache Organization

5-3

5.2.4

Instruction Cache Address Field

Figure 5.2.2 shows the instruction cache address field.

Figure 5.2.2 Instruction Cache Address Field

5.2.5

Instruction Cache Configuration

Each line in the 4 ways of the instruction cache share F1, F0 replacement bits. Figure 5.2.3 shows the

format of replacement bits. These bits are shared by way0, way1, way2 and way3 for 32 KB cache, and

indicate next set to which replacement will be directed; when lock bit is set to 1, indicate this set is not

locked.

Each line of instruction cache data has an associated 26-bit tag that contains a 24-bit physical address,

a single Lock bit and a single Valid bit, except for the line in way0, which has an 25-bit tag that excludes

a Lock bit. Figure 5.2.4 shows the formats of tag and data pair.

Figure 5.2.3 Format of Replacement Bits

Figure 5.2.4 Format of Tag and Data Pair for I-cache

F0: FIFO replace bit 0

F1: FIFO replace bit 1

Format for way0

Format for way1, 2 and 3

P Tag

Data

P Tag

Data

L: Lock bit (1: enable, 0: disable)

V: Valid bit (1: valid, 0: invalid)

PTag: Physical tag (bits 35-12 of the physical address)

Data: Instruction cache data

Cache Tag Index

(8 bits)

Physical Tag

(24 bits )

Word

(2 bits)

Byte

(3 bits)

TMPR4956C Datasheet(PDF) 115 Page - Toshiba Semiconductor