TMPR4956C datasheet(117/286 Pages) TOSHIBA

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Chapter 5 Cache Organization

5-5

Figure 5.2.7 Format of Tag and Data Pair for D-cache

In the processor, the W (write-back) bit, not the cache state, indicates when the primary cache contents

modified data that must be written back to memory. The states Invalid and Dirty Exclusive are used to

describe the cache line. That is, there is no hardware support for cache coherency.

5.3

Lock Function

The lock function can be used to locate critical instruction/data in one instruction/data cache set and they are

not replaced when the Lock bit is set.

5.3.1

Lock Bit Setting and Clearing

Setting the Lock bit in each line cache enable the instruction/data cache lock function. When the lock

function is enabled, the instruction/data in the valid line is locked and never be replaced. The set to be

locked is pointed by FIFO bit. Refilled instruction/data during the lock function is enabled is locked.

When a store miss occurs for the write-through data cache without write allocate, the store data is not

written to the cache and will therefore not be locked.

The lock function is disabled by clearing the Lock bit in each line.

In order to clear or set the Lock bit in the cache, CACHE instructions (Index store I-cache /D-cache

Tag) can be used, and in order to load the instruction/data to cache from memory, another CACHE

instructions (Fill I-cache/D-cache) can be used (refer to CACHE instruction).

Clear the Lock bit as follows when data written to a locked line should be stored in main memory.

Read the locked data from cache memory

Clear the Lock bit

Store the data that was read

Format for way0

Format for way1, 2 and 3

PTag

DATA

PTag

DATA

L: Lock bit (1: enable, 0: disable)

W: Write-back bit (set if cache line has written)

CS: Primary cache state (0: Invalid, 1: Reserved, 2: Reserved, 3: Valid)

PTag: Physical tag (bits 35-12 of the physical address)

Data: Data cache data

TMPR4956C Datasheet(PDF) 117 Page - Toshiba Semiconductor