TMPR4956C datasheet(130/286 Pages) TOSHIBA

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Chapter 8 CPU Exception

8-2

8.3

Priority of Exception

More than one exception may be raised for the same instruction, in which case only the exception with the

highest priority is reported. The TX4956 Processor Core instruction exception priority is shown in Table 8.3.1.

Table 8.3.1 Priority of Exception

Priority

Exception

Mnemonic

ColdReset

SoftReset

NMI

Address error

Inst. Fetch

AdEL

TLB refill

Inst. Fetch

TLBL

TLB invalid

Inst. Fetch

TLBL

Bus error

Inst. Fetch

IBE

Integer overflow, Trap, System Call, Breakpoint,

Reserved Instruction, Coprocessor Unusable, or

Floating-Point Exception

Ov, Tr, Sys,

Bp, RI, CpU,

FPE

Address error

Data access

AdEL/AdES

TLB refill

Data access

TLBL/TLBS

TLB invalid

Data access

TLBL/TLBS

TLB modified

Data write

Mod

Bus error

Data access

DBE

High

Low

Interrupt

Int

General exceptions (i.e., exceptions other than debug exceptions) are prioritized as follows:

If more than one exception condition occurs for a single instruction or a single cycle, only the

exception with the highest priority is reported, as shown in Table 8.3.1 (from highest to lowest

priority).

If two instructions cause exception conditions in the M and E stages of the pipeline simultaneously,

the instruction in the M stage causes the processor to take an exception.

When 64-bit instructions are executed in 32-bit mode, the Reserved Instruction (RI) exception can

occur simultaneous with other exception, as shown below. In that case, the RI exception is given

precedence.

•

RI and CpU

•

RI and Ov

•

RI and AdEL/S (data)

•

RI and TLBL/S (data)

General and debug exceptions are prioritized as follows:

If a general exception condition and a debug exception condition occur for a single instruction, the

debug exception is serviced first, and then the general exception is serviced.

If two instructions cause exception conditions in the M and E stages of the pipeline simultaneously,

only the instruction in the M stage generates an exception.

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