TMPR4956C datasheet(135/286 Pages) TOSHIBA

135 / 286 page

Chapter 8 CPU Exception

8-7

8.8

TLB Refill Exception

8.8.1

Cause

The TLB refill exception occurs when there is no TLB entry to match a reference to a mapped address.

This exception is not maskable.

8.8.2

Processing

There are two special exception vectors for this exception; one for references to 32-bit virtual address,

and one for references to 64-bit virtual address. The KX, SX and UX bits of Status register determine

whether the User, Supervisor or Kernel address referenced are 32-bit mode or 64-bit mode. When EXL bit

of Status register is set to 0, all references use these vectors. When this exception occurs, TLBL or TLBS

code is set in the ExcCode field of Cause register. This code indicates whether the instruction, as shown

by EPC register and BD bit of Cause register, caused the miss by an instruction reference, load operation,

or store operation.

When this exception occurs:

•

BadVAddr, Context, XContext and EntryHi registers hold the virtual address failed address

translation

•

EntryHi register contains ASID from which the translation fault occurred, too

•

A valid address in which to place the replacement TLB entry is contained into Random register

•

The contents of EntryLo register are undefined

If EXL bit of Status register is only set to 0, the following operation is executed. EPC register points to

the address of the instruction causing the exception. If, however, the affected instruction was in the branch

delay slot (for execution during a branch), the immediately preceding branch instruction address is

retained in EPC register and BD bit of Cause register is set to 1.

8.8.3

Servicing

To service this exception, the contents of the Context or XContext register are used as a virtual address

to fetch memory locations containing the physical page frame and access control bits for a pair of TLB

entries. The two entries are placed into the EntryLo0/EntryLo1 register; the EntryHi and EntryLo

registers are written into the TLB.

It is possible that the virtual address used to obtain the physical address and access control information

is on a page that is not resident in the TLB. This condition is processed by allowing a TLB refill exception

in the TLB refill handler. This exception goes to the common exception vector because the EXL bit of the

Status register is set.

TMPR4956C Datasheet(PDF) 135 Page - Toshiba Semiconductor