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TMPR4956C Datasheet(PDF) 139 Page - Toshiba Semiconductor |
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TMPR4956C Datasheet(HTML) 139 Page - Toshiba Semiconductor |
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139 / 286 page ![]() Chapter 8 CPU Exception 8-11 The virtual address of the load and store reference can then be obtained by interpreting the instruction. The physical address can be obtained by using the TLB Probe (TLBP) instruction and reading the EntryLo register to compute the physical page number. The process executing at the time of this exception is handed a bus error signal, which is usually fatal. Note: The bus error treats only the read bus cycle because the TX4956 supports the write buffer. Because the TX4956 supports the non-blocking load and the streaming, please stop the program counter by SYNC instruction or the depending registers instruction, for using EPC register to return from this exception. |
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