TMPR4956C datasheet(141/286 Pages) TOSHIBA

Part #	TMPR4956C

Description	64-Bit TX System RISC TX49 Family

PDF	286 Pages

Scroll/Zoom	100%

Manufacturer	TOSHIBA [Toshiba Semiconductor]

Direct Link	http://www.semicon.toshiba.co.jp/eng

Logo

141 / 286 page

Chapter 8 CPU Exception

8-13

8.13 Trap Exception

8.13.1

Cause

The Trap exception occurs when TGE, TGEU, TLT, TLTU, TEQ, TNE, TGEI, TGEIU, TLTI, TLTIU,

TEQI or TNEI instruction results in a TRUE condition. This exception is not maskable.

8.13.2

Processing

The common exception vector is used for this exception, and the Tr code in Cause register is set.

If EXL bit of Status register is only set to 0, the following operation is executed. EPC register points to

the address of the instruction causing the exception. If, however, the affected instruction was in the branch

delay slot (for execution during a branch), the immediately preceding branch instruction address is

retained in EPC register and BD bit of Cause register is set to 1.

8.13.3

Servicing

The process executing at the time of a Trap exception is handed a floating-point exception signal or

integer overflow signal. This error is usually fatal.

TMPR4956C Datasheet(PDF) 141 Page - Toshiba Semiconductor