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TMPR4956C Datasheet(PDF) 145 Page - Toshiba Semiconductor

Part # TMPR4956C
Description  64-Bit TX System RISC TX49 Family
PDF  286 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 145 Page - Toshiba Semiconductor

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Chapter 8 CPU Exception
8-17
8.17 Coprocessor Unusable Exception
8.17.1
Cause
The Coprocessor Unusable exception occurs when an attempt is made to execute a coprocessor
instruction for either.
•
attempting to execute a coprocessor CPz instruction when its corresponding CUz bit in Status
register.
•
in User or Supervisor mode attempting to execute a CP0 instruction when CU0 bit is cleared to
0. (In Kernel mode, an exception is not raised when a CP0 instruction is issued , regardless of
the CU0 bit setting)
•
an attempt is made to execute a FPU instruction in TX49 without FPU
8.17.2
Processing
The common exception vector is used for this exception, and the CpU code in Cause register is set. The
coprocessor number referred to at the time of the exception is stored in Cause register CE (Coprocessor
Error) field.
If EXL bit of Status register is only set to 0, the following operation is executed. EPC register points to
the address of the instruction causing the exception. If, however, the affected instruction was in the branch
delay slot (for execution during a branch), the immediately preceding branch instruction address is
retained in EPC register and BD bit of Cause register is set to 1.
8.17.3
Servicing
The coprocessor unit to which an attempted reference was mode is identified by the Coprocessor Usage
Error field (CE) of Cause register, which results in one of the following situations:
•
If the process is entitled access to the coprocessor, the coprocessor is marked usable and the
corresponding user state is restored to the coprocessor.
•
If the process is entitled access to the coprocessor, but the coprocessor does not exist or has
failed, interpretation of the coprocessor instruction is possible.
•
If the BD bit is set in the Cause register, the branch instruction must be interpreted; then the
coprocessor instruction can be emulated and execution resumed with the EPC register advanced
past the coprocessor instruction.
•
If the process is not entitled access to the coprocessor, the process executing at the time is
handed an illegal instruction/privileged instruction fault signal. This error is usually fatal.



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