TMPR4956C datasheet(148/286 Pages) TOSHIBA

148 / 286 page

Chapter 8 CPU Exception

8-20

8.20 Exception Handling and Servicing Flowcharts

The remainder of this chapter contains flowcharts for the following three sets of. exceptions and guidelines

for their handlers:

general exceptions and their exception handler

•

Figure 8.20.1 shows general exception handler (HW)

•

Figure 8.20.2 shows general exception servicing guidelines (SW)

TLB/XTLB miss exception and their exception handler

•

Figure 8.20.3 shows TLB/XTLB miss exception handler (HW)

•

Figure 8.20.4 shows TLB/XTLB exception servicing guidelines (SW)

ColdReset, SoftReset and NMI exceptions, and a guideline to their handler.

•

Figure 8.20.5 shows ColdReset, SoftReset & NMI Exception Handling (HW) and Servicing

Guidelines (SW)

Generally speaking, the exceptions are handled by hardware (HW); the exceptions are then serviced by

software (SW).

Figure 8.20.1 General Exception Handler (HW)

EXL

← 1

← 0xFFFF FFFF BFC0 0200 + 180

(unmapped, uncached)

← 0xFFFF FFFF 8000 0000 + 180

(unmapped, cached)

Cause 31 (BD)

← 0

EPC

← PC

Cause 31 (BD)

← 1

EPC

← (PC - 4)

= 1 (bootstrap)

Yes

= 1

Processor forced to Kernel Mode

& interrupt disabled

= 0

Comments

To General Exception Servicing Guidelines

BEV

Instr. in

Br. Dly. Slot?

EXL

(SR1)

Check if exception within

another exception

FP Control/Status Register

is only set if the respective exception

occurs.

EnHi, X/Context are set only for

*TLB- Invalid, Modified,

& Refill exceptions

BadVA is set only for

TLB-invalid, Modified,

and Refill exceptions

Note: not set if it is a Bus Error

Set FP Control Status Resister

EnHi

← VPN2, ASID

X/Context

← VPN2

Set Cause Register

(ExcCode, CE)

Set BadVA

= 0 (normal)

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