TMPR4956C datasheet(153/286 Pages) TOSHIBA

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Chapter 8 CPU Exception

8-25

8.21 Floating-Point Exception of Floating-Point Unit (CP1)

8.21.1

Introduction

This chapter describes floating-point exceptions, including FPU exception type, exception trap

processing, exception flags, saving and restoring state when handling an exception, and trap handlers for

IEEE Standard 754 exceptions.

8.21.2

Exception Types

The FP Control/Status register described in Chapter 3 contains an Enable bit for each exception type;

exception Enable bits determine whether an exception will cause the FPU to initiate a trap or set a status

flag.

•

If a trap is taken, the FPU remains in the state found at the beginning of the operation and a

software exception handling routine executes.

•

If no trap is taken, an appropriate value is written into the FPU destination register and

execution continues.

The FPU supports the five IEEE Standard 754 exceptions:

•

Inexact (I)

•

Underflow (U)

•

Overflow (O)

•

Division by Zero (Z)

•

Invalid Operation (V)

Cause bits, Enables, and Flag bits (status flags) are used.

The FPU adds a sixth exception type, Unimplemented Operation (E). This exception indicates the use

of a software implementation. The Unimplemented Operation exception has no Enable or Flag bit;

whenever this exception occurs, an unimplemented exception trap is taken.

Figure 8.21.1 shows the Control/Status register bits that support exceptions.

Bit #

Cause Bits

Bit #

Enable Bits

Bit #

Flag Bits

Unimplemented

Invalid

Division by

Zero

Overflow

Underflow

Inexact

Figure 8.21.1 Control/Status Register (Exception/Flag/Trap/Enable Bits)

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