TMPR4956C datasheet(155/286 Pages) TOSHIBA

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Chapter 8 CPU Exception

8-27

Table 8.21.2 FPU Exception-Causing Conditions

FPA Internal

Result

IEEE Standard

754

Trap Enable

Trap Disable

Notes

Inexact result

Loss of accuracy

Exponent overflow

O, I

(Note 1)

O, I

Normalized exponent > Emax

Division by zero

Zero is (exponent = Emin – 1, mantissa = 0)

Overflow on convert

Source out of integer range

Signaling NaN source

(Note 2)

Quiet NaN result generated from quiet NaN

source

Invalid operation

0/0, etc.

Exponent underflow

Normalized exponent < Emin

Denormalized or

QNaN

None

Denormalized is (exponent = Emin – 1 and

mantissa < > 0)

Note 1: The IEEE Standard 754 specifies an inexact exception on overflow only if the overflow trap is

disabled.

Note 2: If the conversion is to integer, it occurs the E-exception on Signaling NaN source.

8.21.5

FPU Exceptions

The following sections describe the conditions that cause the FPU to generate each of its exceptions,

and details the FPU response to each exception-causing condition.

Inexact Exception (I)

The FPU generates the Inexact exception if one of the following occurs:

•

the rounded result of an operation is not exact, or

•

the rounded result of an operation overflows, or

•

the rounded result of an operation underflows and both the Underflow and Inexact Enable bits

are not set and the FS bit is set.

Trap Enabled Results: If Inexact exception traps are enabled, the result register is not modified and

the source registers are preserved.

Trap Disabled Results: The rounded or overflowed result is delivered to the destination register if no

other software trap occurs.

Invalid Operation Exception (V)

The Invalid Operation exception is signaled if one or both of the operands are invalid for an

implemented operation. When the exception occurs without a trap, the MIPS ISA defines the result as a

quiet Not a Number (qNaN). The invalid operations are:

•

Addition or subtraction: magnitude subtraction of infinities, such as: (

+∞) + (–∞) or (–∞) – (–∞)

•

Multiplication: 0 times

∞, with any signs

•

Division: 0/0, or

∞/∞, with any signs

•

Comparison of predicates involving ‘<’ or ‘>’ without ‘?’, when the operands are unordered

•

Any arithmetic operation, when one or both operands is a signaling NaN. A move (MOV)

operation is not considered to be an arithmetic operation, but absolute value (ABS) and negate

(NEG) are.

•

Comparison or a Convert From Floating-point Operation on a signaling NaN.

•

Square root:

x , where x is less than zero.

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