TMPR4956C datasheet(159/286 Pages) TOSHIBA

159 / 286 page

Chapter 9 Initialization Interface

9-1

Initialization Interface

This chapter describes the TX4956 Initialization interface, and the processor modes. This includes the reset

signal description and types, and initialization sequence, with signals and timing dependencies, and the user-

selectable TX4956 processor modes.

Low-active signals are indicated by a trailing asterisk, such as ColdReset*, the power-on/cold reset signal.

9.1

Functional Overview

The TX4956 processor has the following three types of resets; they use the PLLReset*, ColdReset* and

Reset* input signals.

•

PLLReset* signal is asserted to initialize the Clock Generator. (CG)

•

ColdReset* signal is asserted after the power supply is stable and then restarts all clocks. A cold

reset completely reinitializes the internal state machine of the processor without saving any state

information.

•

Reset* signal is asserted to generate SoftReset exception. Clock ratio is not changed (DivMode is

not reloaded). The internal state except certain registers is not saved.

After reset, the processor is bus master and drives the SysAD bus.

For reset vector address, use 0xbfc0 0000.

In the TX4956 processor core, the reset vector is located in uncached and unmapped address space.

Therefore, the cache and TLB need not be initialized at reset processing.

9.1.1

System Coordination

Care must be taken to coordinate system reset with other system elements. In general, bus errors

immediately before, during, or after a reset may result in unpredicted behavior. Also, a small amount of

processor state is guaranteed as stable after a reset of the TX4956 processor, so extreme care must be

taken to correctly initialize the processor through software.

TMPR4956C Datasheet(PDF) 159 Page - Toshiba Semiconductor