TMPR4956C datasheet(157/286 Pages) TOSHIBA

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Chapter 8 CPU Exception

8-29

The MIPS architecture requires that loss of accuracy be detected as an inexact result.

Trap Enabled Results:

If Underflow or Inexact traps are enabled, or if the FS bit is not set, then an

Unimplemented exception (E) is generated, and the result register is not

modified.

Trap Disabled Results:

If Underflow and Inexact traps are not enabled and the FS bit is set, the result

is determined by the rounding mode and the sign of the intermediate result.

Unimplemented Instruction Exception (E)

Any attempt to execute an instruction with an operation code or format code that has been reserved for

future definition sets the Unimplemented bit in the Cause field in the FPU Control/Status register and

traps. The operand and destination registers remain undisturbed and the instruction is emulated in

software. Any of the IEEE Standard 754 exceptions can arise from the emulated operation, and these

exceptions in turn are simulated.

The Unimplemented Instruction exception can also be signaled when unusual operands or result

conditions are detected that the implemented hardware cannot handle properly. These include:

•

Denormalized operand, except for Compare instruction

•

Quiet Not a Number operand, except for Compare instruction

•

Denormalized result or Underflow, when either Underflow or Inexact Enable bits are set or the

FS bit is not set.

•

Reserved opcodes

•

Unimplemented formats

•

Operations which are invalid for their format (for instance, CVT.S.S)

Note:

Denormalized and NaN operands are only trapped if the instruction is a convert or

computational operation. Moves do not trap if their operands are either denormalized or

NaNs.

The use of this exception for such conditions is optional; most of these conditions are newly developed

and are not expected to be widely used in early implementations. Loopholes are provided in the

architecture so that these conditions can be implemented with assistance provided by software,

maintaining full compatibility with the IEEE Standard 754.

Trap Enabled Results: The result register is not modified, and the source registers are preserved.

Trap Disabled Results: This trap cannot be disabled.

TMPR4956C Datasheet(PDF) 157 Page - Toshiba Semiconductor