TMPR4956C datasheet(160/286 Pages) TOSHIBA

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Chapter 9 Initialization Interface

9-2

9.2

Reset Signal Description

This section describes the three reset signals, PLLReset*, ColdReset* and Reset*.

•

PLLReset*:

Assertion of PLLReset* signal initializes the on-chip PLL. PLLReset* signal should

be asserted, for example, when the system power is turned on.

•

ColdReset*:

The ColdReset* signal must be asserted to reset the processor. Internal clock begins

to cycle and is synchronized with the deasserted edge of ColdReset* signal.

ColdReset* signal can be asserted and deasserted asynchronously with the rising

edge of MasterClock.

•

Reset*:

The Reset* signal must be asserted to generate SoftReset exception. Keep Reset*

signal to be deasserted when a soft reset is not used.

9.2.1

Power-On Reset

Power-on reset is a reset that occurs when the system power is turned on. This reset initializes the

PLL inside the on-chip Clock Generator. After MasterClock became stable and the PLL stabilization

time has elapsed, PLLReset* must be deasserted and then ColdReset* must be deasserted.

Figure 9.2.1 illustrates the power-on reset timing.

Figure 9.2.1 Power-On Reset Timing

MasterClock & PLL Stabilization Time

≥ 10 ms

VCC IO

VCC Int

MasterClock

(MClk)

Wavy lines indicate one or more identical

cycles, not shown due to space constraints.

ColdReset*

≥ 1 ms

PLLReset*

GBUSCLK

(Internal Clock)

Note: PLLReset* need not be synchronized to MasterClock.

PLLReset* is sampled by the on-chip logic.

Reset*

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