TMPR4956C datasheet(277/286 Pages) TOSHIBA

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Chapter 17 Electrical Characteristics

17-3

17.1.4

AC Characteristics

17.1.4.1 Clock Timing

TC = −20°C to 85°C, VCCInt = 1.25 V ± 5%, VCCIO = 3.3 V ± 0.2 V or 2.5 V ± 0.2 V

Parameter

Symbol

Conditions

Min

Max

Units

MasterClock High Width

tMCH

Transition

≤ 2 ns

⎯

MasterClock Low Width

tMCL

Transition

≤ 2 ns

⎯

MasterClock Frequency

(Note 1)

fMCK

133

MHz

Internal Operation Frequency

⎯

Products for

400 MHz

133

400

MHz

MasterClock Period

tMCP

⎯

7.5

MasterClock Rise Time

tMCR

⎯

MasterClock Fall Time

tMCF

⎯

Note 1: Operation of the TX4956C is only guaranteed with the Phase Lock Loop enabled.

Note 2: All output timings assume a 25-pF capacitive load.

17.1.4.2 System Interface

TC = −20°C to 85°C, VCCInt = 1.25 V ± 5%, VCCIO = 3.3 V ± 0.2 V

Parameter

Symbol

Conditions

Min

Max

Units

BufSel = 0 100%

(16-mA buffer)

1.0

(Note 4)

4.0

Data Output

(Note 1, 2, 3)

tDO

BufSel = 1 50%

(8-mA buffer)

1.0

(Note 4)

4.5

Data Setup

(Note 3)

tDS

⎯

2.3

⎯

Data Hold

(Note 3)

tDH

⎯

0.5

⎯

TC = −20°C to 85°C, VCCInt = 1.25 V ± 5%, VCCIO = 2.5 V ± 0.2 V

Parameter

Symbol

Conditions

Min

Max

Units

BufSel = 0 100%

(16-mA buffer)

1.0

(Note 4)

4.5

Data Output

(Note 1, 2, 3)

tDO

BufSel = 1 50%

(8-mA buffer)

1.0

(Note 4)

5.0

Data Setup

(Note 3)

tDS

⎯

2.5

⎯

Data Hold

(Note 3)

tDH

⎯

0.5

⎯

Note 1: Timings are measured from 1.5 V of MasterClock to 1.5 V of each signal.

Note 2: Capacitive load for all output timings is 25 pF.

Note 3: Applies to all system interface signals.

Note 4: Offers a guarantee of design.

17.1.5

Timing Diagrams

17.1.5.1 Clock Timing

tMCH

tMCL

tMCR

tMCF

tMCP

tMCM

tMCL

0.8 *VCCIO

0.2 *VCCIO

1.5 V

MasterClock

TMPR4956C Datasheet(PDF) 277 Page - Toshiba Semiconductor

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