TMPR4956C datasheet(285/286 Pages) TOSHIBA

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Appendix B Movement parameter setting of a processor

B-1

Appendix B. Movement parameter setting of a processor

A table explains movement parameter with a processor.

Item

Description

Writeback protocol

These modes are selected by G2SConfig-Register.

Writeback data rate

These modes are selected by G2SConfig-Register.

Clock multiplier

(Clock ratio of MasterClock)

These modes are selected by external pin (DivMode[2:0]) which are loaded at

Power-on or deasserting of ColdReset*.

Endian set

Endian is selected by external pin (Endian) which are loaded at Power-on or

deasserting of ColdReset*.

0: Little Endian

1: Big Endian

Timer Interrupt

Timer-Interrupt is selected by external pin (TintDis).

0: Timer-Interrup is enable

1: Timer-Interrupt is disable

SysAD bus width

SysAD bus width is selected by external pin (BSIZE64*).

0: 64-bit external bus width

1: 32-bit external bus width

SysAD bus protocol type

SysAD bus protocol type is selected by external pin (MODE43*) which are loaded

at Power-on or deasserting of ColdReset*.

0: R4300 type (only support 32-bit external bus width)

1: R5000 type

Note 1: Address (32-bit), D: Double Word (64-bit), W: Word (32-bit), x:Idle cycle

Note 2: Initial set of data rate

Single write:

64-bit width ADxx (R4000 compatible), 32-bit width AWxx

Block write:

64-bit width ADDDD, 32-bit width AWWWWWWWW

R4000 compatible

64-bit:ADxx

32-bit:AWxx

Reserved

reserved

Reissue write

64-bit:AD

32-bit:AW

Write mode

Pipeline write

64-bit:AD

32-bit:AW

Consecutive

translation

64-bit:ADDDD

32-bit:AWWWWWWW

Date rate

Dummy cycle

64-bit:ADxxDxxDxxDxx

32-bit:AWxxWxxWxxWxx

WxxWxxWxxWxx

DivMode[2:0]

EC-bit

ratio

000

010

1:4

001

111

1:2.5

010

000

1:2

011

001

1:3

100

1:3.5

101

1:4.5

110

1:5

111

011

1:6

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