 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AM69 Datasheet(PDF) 137 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AM69 Datasheet(HTML) 137 Page - Texas Instruments |
|
|
137 / 326 page  5.3.31.2 Clock Table 5-114. Clock0 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] AND PIN [4] WKUP_LF_CLKIN I Low Frequency (32.768 KHz) Oscillator Input M34 A18 WKUP_OSC0_XI I High Frequency Oscillator Input T38 A24 WKUP_OSC0_XO O High Frequency Oscillator Output U37 B25 Table 5-115. Clock1 Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] AND PIN [4] OSC1_XI I High Frequency Oscillator Input P38 B23 OSC1_XO O High Frequency Oscillator Output N37 A22 5.3.31.3 System Table 5-116. MCU System Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] AND PIN [4] MCU_CLKOUT0 OZ Reference clock output for Ethernet PHYs (50MHz or 25MHz) M38 B21 MCU_EXT_REFCLK0 I External system clock input L33, M33 A20, B18 MCU_OBSCLK0 O Observation clock output for test and debug purposes only H34, M38 B21, E17 MCU_PORz I MCU Domain Cold Reset K32 C24 MCU_RESETSTATz O MCU Domain Warm Reset status output F36 E21 MCU_RESETz I MCU Domain Warm Reset G36 E20 MCU_SAFETY_ERRORn IO Error signal output from MCU Domain ESM N36 C22 MCU_SYSCLKOUT0 O MCU Domain system clock output for test and debug purposes only L33 B18 Table 5-117. System Signal Descriptions SIGNAL NAME [1] PIN TYPE [2] DESCRIPTION [3] ALY PIN [4] AND PIN [4] AUDIO_EXT_REFCLK0 IO External clock routed to ATL or McASP as one of the selectable input clock sources, or as a output clock output for ATL or McASP AJ34 T30 AUDIO_EXT_REFCLK1 IO External clock routed to ATL or McASP as one of the selectable input clock sources, or as a output clock output for ATL or McASP AH37 F33 EXTINTn I External Interrupt AN35 Y29 EXT_REFCLK1 I External clock input to Main Domain, routed to Timer clock muxes as one of the selectable input clock sources for Timer/WDT modules, or as reference clock to MAIN_PLL2 (PER1 PLL) AJ32 J33 GPMC0_FCLK_MUX O GPMC functional clock output selected through a mux logic AF36 K33 OBSCLK0 O Observation clock output for test and debug purposes only AN37 W30 OBSCLK1 O Observation clock output for test and debug purposes only AG37 H32 PMIC_POWER_EN1 O Power enable output for MAIN Domain supplies L38 B16 PMIC_WAKE0n O PMIC WakeUp (active low) AJ34 T30 PMIC_WAKE1n O PMIC WakeUp (active low) M33 A20 PORz I SoC PORz Reset Signal P33 D24 www.ti.com AM69A, AM69 SPRSP92D – FEBRUARY 2023 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 137 Product Folder Links: AM69A AM69 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
