ACT8870 datasheet(23/49 Pages) QORVO

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ACT8870

Advanced PMU for Microcontrollers

and Solid State Drive Applications

Data Sheet Rev. 7.0, Feb. 18, 2020 | Subject to change without notice

23 of 49

www.qorvo.com

RESET State

In the RESET, or “cold” state, the ACT8870 is waiting

for the input voltage on VIN to be within a valid range

defined by I2C bits POK_OV_SET and POK_UV_SET.

All

regulators

are

off

RESET.

nRESET,

nRESET_AUX1, and nRESET_AUX2 are asserted low.

All volatile registers are reset to defaults and Non-Vola-

tile registers are reset to programmed defaults. The IC

transitions from RESET to ACTIVE when the input

voltage enters the valid range. The IC transitions from

any other state to RESET if the input voltage drops

below the UVLO threshold voltage.

ACTIVE State

The ACTIVE state is the normal operating state when

the input voltage is within the allowable range, all

outputs are turned on, and no faults are present. When

entering the ACTIVE state from the RESET state, all

regulators are powered on following their programmed

power up sequence. The regulators are not sequenced

when entering ACTIVE from SLEEP.

SLEEP State

The SLEEP state is a low power mode for the operating

system. Each output can be programmed to be on or off

in the SLEEP state. The outputs do not follow any

sequencing when turning on or off as they enter or exit

the SLEEP state. They do turn on with their

programmed

softstart

time.

Buck1/2/3/4

can

programmed to regulate to their VSET0 voltage, VSET1

voltage, or be turned off in the SLEEP state. LDO1/2/3

can be programmed to regulate to their VSET0 voltage

or can be programmed to be turned off.

Note that

LDO1/2/3 do not have a VSET1 voltage.

The IC can enter SLEEP via a hardware input pin or an

I2C command.

The hardware input is typically the

PWREN pin, but this can be reconfigured to other pins.

To enable SLEEP via I2C, program the following:

Set register 0x08h bit1 (PWR_DN_MODE) = 1

Set register 0x00h bit0 (PWRDN_EN) = 1

enter

SLEEP,

program

0x01h

bit1

(SLP_ENTR) = 1.

I2C is disabled in SLEEP mode, to the only way to exit

SLEEP mode is to toggle the PWREN pin.

THERMAL State

In the THERMAL state the chip has exceeded the ther-

mal shutdown temperature. To protect the device, all

the regulators are shut down and all three nRESETx

pins are asserted low. This state can be disabled by

setting register 0x0Ah bit4 (TSD_nMASK) = 0. Note

that thermal shutdown fault flag, TSD_SHUTDWN, still

provides the thermal status even TSD_nMASK = 0.

OVUVFLT State

In the OVUVFLT state one of the regulators has exceed

an OV level at any time or UV level after the soft start

ramp has completed. All regulators shutdown and all

three nRESETx outputs are asserted low when the IC

enters OVUVFLT state. The OVUVFLT state is timed to

retry after 100ms and enter the ACTIVE state. If the OV

or UV condition still exists in the ACTIVE state the IC

returns back to the OVUVFLT state. The cycle contin-

ues until the OV or UV fault is removed or the input

power is removed. This state can be disabled by setting

the OV_nMASK or UV_nMASK non-volatile bits low.

The IC does not directly enter OVUVFLT in an

overcurrent condition, but does enter this state due to

the resulting UV condition.

Figure 3. State Machine

Sequencing

The ACT8870 provides the end user with extremely

versatile sequencing capability that can be optimized for

many different applications. Each of the seven outputs

has four basic sequencing parameters: input trigger,

turn-on delay, softstart time, and output voltage. Each of

these parameters is controlled via the ICs internal

registers. As an example, the ACT8870QJ101-T

sequencing and output voltages are optimized for the

Atmel SAMA5D3D3 processor. The specifics for this IC

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