ACT8870 datasheet(24/49 Pages) QORVO

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ACT8870

Advanced PMU for Microcontrollers

and Solid State Drive Applications

Data Sheet Rev. 7.0, Feb. 18, 2020 | Subject to change without notice

24 of 49

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as well as others are detailed at the end of the datasheet.

Contact sales@active-semi.com for custom sequencing

configurations. Refer to the Active-Semi Application

Note describing the Register Map for full details on I2C

functionality and programming ranges.

Input Trigger. The input trigger for a regulator is the

event that turns that regulator on. Each output can have

a separate input trigger. The input trigger can be the

internal power ok (POK) signal from one of the other

regulators, the internal VIN POK signal, or an external

signal applied to an input pin such as EXT_PG or GPIO.

This flexibility allows a wide range of sequencing

possibilities, including have some of the outputs be

sequenced with another external power supply or a

control signal from the host. As an example, if the LDO1

input trigger is Buck1, LDO1 will not turn on until Buck1

is in regulation. Input triggers are defined at the factory

and can only be changed with a custom CMI

configuration. The nRESETx, POK, PG, and EXT_EN

outputs can be connected to a power supply’s internal

POK signal and used to trigger external supplies in the

overall sequencing scheme.

Turn-on Delay. The turn-on delay is the time between

an input trigger going active and the output starting to

turn on. Each output’s turn-on delay is configured via its

I2C bit ONDLY. Turn-on delays can be changed after the

IC is powered on, but they are volatile and reset to the

factory defaults when power is recycled.

Softstart Time. The softstart time is the time it takes an

output to ramp from 0V to its programmed voltage. Each

output’s softstart time is configured via its I2C bit

SS_RAMP. Softstart times can be changed after the IC

is powered on, but they are volatile and reset to the

factory defaults when power is recycled.

Output Voltage. The output voltage is each regulator’s

desired

voltage.

Each

buck’s

output

voltage

programmed via its I2C bits Bx_VSET0 and Bx_VSET1.

The output regulates to Bx_VSET0 in ACTIVE mode.

They can be programmed to regulate to Bx_VSET1 in

DVS mode or SLEEP mode. Each output’s voltage can

be changed after the IC is powered on, but the new

setting is volatile and is reset to the factory defaults

when power is recycled. Output voltages can be

changed on the fly. If a large output voltage change is

required, it is best to make multiple smaller changes.

This prevents the IC from detecting an instantaneous

over or under voltage condition because the fault

threshold are immediately changed, but the output

takes time to respond.

Dynamic Voltage Scaling

On-the-fly dynamic voltage scaling (DVS) for the four

buck converters is available via the I2C interface. This

allows systems to save power by quickly adjusting the

microprocessor performance level when the workload

changes. Note that DVS is not a different operating

state. The IC operates in the ACTIVE state, but just

regulates the outputs to a different voltage. For fault free

operation, the user must ensure output load conditions

plus the current required to charge the output

capacitance during a DVS rising voltage condition does

not exceed the current limit setting of the regulator.

As with any power supply, changing an output voltage

too fast can require a current higher than the current

limit setting. The user must ensure that the voltage

step, slew rate, and load current conditions do not

result in an instantaneous loading that results in a

current limit condition.

Enter DVS by programming register 0x00h bit1

(DVS_EN) = 1 and then pulling the EXT_EN pin high.

Note that some CMI configurations may not require

DVS_EN = 1 and may use different input pins.

Fault Protection

The ACT8870 contains several levels of fault protection,

including the following:

Output Overvoltage

Output Undervoltage

Output Current Limit

Thermal Warning

Thermal Shutdown

There are three types of I2C register bits associated with

each fault condition: fault flag bits, fault bits, and mask

bits. The fault flag bits display the real-time fault status.

Their status is valid regardless of whether or not that

fault is masked. The mask bits either block or allow the

fault to affect the fault bit. Each potential fault condition

can be masked via I2C if desired. Any unmasked fault

condition results in the fault bit going high, which asserts

the IRQ pin. IRQ is typically active low. The IRQ pin

only de-asserts after the fault condition is no longer

present and the corresponding fault bit is read via I2C.

Note that masked faults can still be read in the fault flag

bit. Refer to Active-Semi Application Note describing the

programming ranges.

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