DSP56721 datasheet(25/54 Pages) FREESCALE

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

Start condition hold time

THD;STA

4.0

–

0.6

–

μs

SCL low period

TLOW

4.7

–

1.3

–

μs

SCL high period

THIGH

4.0

–

1.3

–

μs

SCL and SDA rise time

–

5.0

–

5.0

SCL and SDA fall time

–

5.0

–

5.0

Data set-up time

TSU;DAT

250

–

100

–

Data hold time

THD;DAT

0.0

–

0.0

0.9

μs

DSP clock frequency

• Filters bypassed

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

FOSC

10.6

11.8

13.1

–

28.5

39.7

61.0

–

MHz

SCL low to data out valid

TVD;DAT

–

3.4

–

0.9

μs

Stop condition setup time

TSU;STO

4.0

–

0.6

–

μs

HREQ in deassertion to last SCL edge

(HREQ in set-up time)

tSU;RQI

0.0

–

0.0

–

First SCL sampling edge to HREQ output

deassertion2

• Filters bypassed

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

TNG;RQO

× T

C + 30

× T

C + 50

× T

C + 130

× T

C + 230

–

50.0

70.0

250.0

150.0

–

50.0

70.0

150.0

250.0

Last SCL edge to HREQ output not

deasserted2

• Filters bypassed

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

TAS;RQO

× T

C + 30

× T

C + 40

× T

C + 80

× T

C + 130

140

–

140

–

HREQ in assertion to first SCL edge

• Filters bypassed

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

TAS;RQI

4327

4317

4282

4227

–

927

917

877

827

–

First SCL edge to HREQ is not asserted

(HREQ in hold time.)

tHO;RQI

0.0

–

0.0

–

Notes:

VCORE_VDD = 1.00± 0.10 V; TJ = -40°C to 125°C; CL = 50 pF.

Pull-up resistor: R P (min) = 1.5K Ohms.

Capacitive load: C b (max) = 50 pF.

All times assume noise free inputs.

All times assume internal clock frequency of 200 MHz.

SHI_1 specs match those of SHI.

Table 12. SHI I2C Protocol Timing Parameters (Continued)

Standard I2C

No.

Characteristics1,2,3,4,5

Symbol/

Expression

Standard

Fast-Mode

Unit

Min

Max

Min

Max

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