DSP56721 datasheet(28/54 Pages) FREESCALE

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

SCKT rising edge to FST out (wr) high6

––

–

20.0

10.0

x ck

i ck

SCKT rising edge to FST out (wr) low6

––

–

22.0

12.0

x ck

i ck

SCKT rising edge to FST out (wl) high

–

19.0

9.0

x ck

i ck

SCKT rising edge to FST out (wl) low

–

20.0

10.0

x ck

i ck

SCKT rising edge to data out enable from high

impedance

––

–

22.0

17.0

x ck

i ck

SCKT rising edge to transmitter #0 drive enable

assertion

––

–

17.0

11.0

x ck

i ck

SCKT rising edge to data out valid

–

18.0

13.0

x ck

i ck

SCKT rising edge to data out high impedance7

––

–

21.0

16.0

x ck

i ck

SCKT rising edge to transmitter #0 drive enable

deassertion7

––

–

14.0

9.0

x ck

i ck

FST input (bl, wr) setup time before SCKT falling edge6

––

2.0

18.0

–

x ck

i ck

FST input (wl) setup time before SCKT falling edge

–

2.0

18.0

–

x ck

i ck

FST input hold time after SCKT falling edge

–

4.0

5.0

–

x ck

i ck

FST input (wl) to data out enable from high impedance

–

21.0

–

FST input (wl) to transmitter #0 drive enable assertion

–

14.0

–

Flag output valid after SCKT rising edge

–

14.0

9.0

x ck

i ck

Table 13. Enhanced Serial Audio Interface Timing Parameters (Continued)

No.

Characteristics1, 3, 4

Symbol

Expression5

Min

Max

Condition2 Unit

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