DSP56721 datasheet(14/54 Pages) FREESCALE

14 / 54 page

SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

2.1.8

Reset, Stop, Mode Select, and Interrupt Timing

For reset, stop, mode select, and interrupt timing, see Table 9.

EXTAL input low1

(40% to 60% duty cycle)

• Crystal oscillator

• Square wave input

Etl

16.67

2.5

100

inf

EXTAL cycle time

• With PLL disabled

• With PLL enabled

Etc

33.3

inf

500

Instruction cycle time

• With PLL disabled

• With PLL enabled

5.00

inf

5120

Notes:

Measured at 50% of the input transition.

The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock

high or low time required for correct operation, however, remains the same at lower operating frequencies;

therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle

as long as the minimum high time and low time requirements are met.

A valid clock signal must be applied to the EXTAL pin within 3 ms of the DSP56720/DSP56721 being

powered up.

Table 9. Reset, Stop, Mode Select, and Interrupt Timing Parameters

No.

Characteristics

Expression

Min

Max

Unit

Delay from RESET assertion to all pins at reset value3

–

Required RESET duration4

• Power on, external clock generator, PLL disabled

• Power on, external clock generator, PLL enabled

2 x TC

–

Syn reset deassert delay time

• Minimum

× T

–

• Maximum (PLL enabled)

(2 x TC)+TLOCK

200

–

Mode select setup time

–

10.0

–

Mode select hold time

–

10.0

–

Minimum edge-triggered interrupt request assertion width

–

Minimum edge-triggered interrupt request deassertion width

–

Delay from interrupt trigger to interrupt code execution

× T

C + 4

–

Table 8. Clock Operation (Continued)

No.

Characteristics

Symbol

Min

Max

Units

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