DSP56721 datasheet(27/54 Pages) FREESCALE

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

2.2.4

Enhanced Serial Audio Interface (ESAI) Timing

See Table 13 For ESAI timing parameters and Figure 20, Figure 21, Figure 22, and Figure 23 for timing diagrams.

Table 13. Enhanced Serial Audio Interface Timing Parameters

No.

Characteristics1, 3, 4

Symbol

Expression5

Min

Max

Condition2 Unit

Clock cycle5

tSSICC

× T

× Tc

20.0

–

i ck

Clock high period

• For internal clock

–

× T

–

• For external clock

× Tc

–

Clock low period

• For internal clock

–

× T

–

• For external clock

× Tc

–

SCKR rising edge to FSR out (bl) high

–

17.0

7.0

x ck

i ck a

SCKR rising edge to FSR out (bl) low

–

17.0

7.0

x ck

i ck a

SCKR rising edge to FSR out (wr) high6

––

–

19.0

9.0

x ck

i ck a

SCKR rising edge to FSR out (wr) low6

––

–

19.0

9.0

x ck

i ck a

SCKR rising edge to FSR out (wl) high

–

16.0

6.0

x ck

i ck a

SCKR rising edge to FSR out (wl) low

–

17.0

7.0

x ck

i ck a

Data in setup time before SCKR (SCK in synchronous

mode) falling edge

––

12.0

19.0

–

x ck

i ck

Data in hold time after SCKR falling edge

–

3.5

9.0

–

x ck

i ck

FSR input (bl, wr) high before SCKR falling edge 6

––

2.0

12.0

–

x ck

i ck a

FSR input (wl) high before SCKR falling edge

–

2.0

12.0

–

x ck

i ck a

FSR input hold time after SCKR falling edge

–

2.5

8.5

–

x ck

i ck a

Flags input setup before SCKR falling edge

–

0.0

19.0

–

x ck

i ck s

Flags input hold time after SCKR falling edge

–

6.0

0.0

–

x ck

i ck s

SCKT rising edge to FST out (bl) high

–

18.0

8.0

x ck

i ck

SCKT rising edge to FST out (bl) low

–

20.0

10.0

x ck

i ck

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