DSP56721 datasheet(32/54 Pages) FREESCALE

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

Figure 23. ESAI HCKR Timing

2.2.5

Timer Timing

See Table 14 for timer timing parameters and Figure 24 for the timing diagram.

Figure 24. TIO Timer Event Input Restrictions Diagram

2.2.6

GPIO Timing

See Table 15 for general purpose input and output (GPIO) timing and Figure 25 for the timing diagram.

Table 14. Timer Timing Parameters

No.

Characteristics

Expression

Unit

Min

Max

TIO Low

× T

C + 2.0

12.0

–

TIO High

× T

C + 2.0

12.0

–

Notes:

VCORE_VDD = 1.00 V ± 0.10 V; TJ = -40°C to 125°C, CL = 50 pF

TIMER_1 specs match those of TIMER

Table 15. GPIO Timing Parameters

No.

Characteristics1

Expression

Min

Max

Unit

100

Fsys edge to GPIO out valid (GPIO out delay time)2

––

101

Fsys edge to GPIO out not valid (GPIO out hold time)2

––

102

Fsys In valid to EXTAL edge (GPIO in set-up time)2

–2

–

103

Fsys edge to GPIO in not valid (GPIO in hold time)2

–0

–

104

Minimum GPIO pulse high width

2 x TC

–

HCKR

SCKR

(Output)

TIO

DSP56721 Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc

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