DSP56721 datasheet(29/54 Pages) FREESCALE

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

HCKR/HCKT clock cycle

–

2 x TC

–

HCKT input rising edge to SCKT output

–

18.0

–

HCKR input rising edge to SCKR output

–

18.0

–

Notes:

VCORE_VDD = 1.00 ± 0.10 V; TJ = -40°C to 125°C; CL = 50 pF.

i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(Asynchronous implies that SCKT and SCKR are two different clocks.)

i ck s = internal clock, synchronous mode

(Synchronous implies that SCKT and SCKR are the same clock.)

bl = bit length

wl = word length

wr = word length relative

SCKT(SCKT pin) = transmit clock

SCKR(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

For the internal clock, the external clock cycle is defined by Tc and the ESAI control register.

The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal

waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit

clock of the first word in frame.

Periodically sampled and not 100% tested.

ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.

Table 13. Enhanced Serial Audio Interface Timing Parameters (Continued)

No.

Characteristics1, 3, 4

Symbol

Expression5

Min

Max

Condition2 Unit

DSP56721 Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc

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