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DSP56721 Datasheet(PDF) 42 Page - Freescale Semiconductor, Inc |
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DSP56721 Datasheet(HTML) 42 Page - Freescale Semiconductor, Inc |
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42 / 54 page ![]() SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 42 Figure 35. HDI24 Host DMA Read Timing Diagram 2.2.10 S/PDIF Timing See Table 19 for Sony/Philips Digital Interconnect Format (S/PDIF) timing parameters and Figure 36 and Figure 37 for timing diagrams. Table 19. S/PDIF Timing Parameters Characteristics Symbol All Frequency Unit Min Max SPDIFIN1, SPDIFIN2, SPDIFIN3, SPDIFIN4 Skew: asynchronous inputs, no specs apply –– 0.7 ns SPDIFOUT1,SPDIFOUT2 output (Load = 50 pf) •Skew • Transition Risng • Transition Falling – – – – – – 1.5 24.2 31.3 ns SPDIFOUT1, SPDIFOUT2 output (Load = 30 pf) •Skew • Transition Risng • Transition Falling – – – – – – 1.5 13.6 18.0 ns SRCK period srckp 40.0 – ns SRCK high period srckph 16.0 – ns SRCK low period srckpl 16.0 – ns STCLK period stclkp 40.0 – ns STCLK high period stclkph 16.0 – ns STCLK low period stclkpl 16.0 – ns 326 317 318 327 328 329 HOREQ (Output) HACK (Input) H0-H23 (Output) Data Valid RXH Read 342 342 343 |
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