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DSP56721 Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc |
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DSP56721 Datasheet(HTML) 47 Page - Freescale Semiconductor, Inc |
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47 / 54 page ![]() SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1 Freescale Semiconductor 47 Figure 40. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 8) LAD[23:0] output setup from LCLK Tad_s 18 – ns LAD[23:0] output hold from LCLK Tad_h 17 – ns LCLK to output high impedance for LAD[23:0] Tad_z –19 ns Notes: 1. A negative hold time means that the signal could be invalid before the LCLK rising edge. Table 22. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8) (Continued) Parameter Symbol Min Max Unit Tin_s Tin_h LGTA asynchronous input LA[2:0]/LBCTL/LCS[7:0] LOE/LWE LCKE/LSDA10/LSDDQM LGPL[5:0] Output Signals LCLK LAD[23:0] (data) Tclk LUPWAIT asynchronous input Tgta Tupwait Tout_s Tout_h LALE Tad_s Tad_h LAD[23:0] Tad_z LSDWE/LSDRAS/LSDCAS Tale Tale_h |
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