DSP56721 datasheet(20/54 Pages) FREESCALE

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

First SCK sampling edge to HREQ output

deassertion

Slave

Bypassed

–

Very Narrow

–

Narrow

–

Wide

–

145

–

Last SCK sampling edge to HREQ output

not deasserted (CPHA = 1)

Slave

Bypassed

–

50.0

–

Very Narrow

–

60.0

–

Narrow

–

100.0

–

Wide

–

150.0

–

SS deassertion to HREQ output not

deasserted (CPHA = 0)

Slave

–

45.0

–

SS deassertion pulse width (CPHA = 0)

Slave

–

TC + 6

11.0

–

HREQ in assertion to first SCK edge

Master

–

0.5 x TSPICC + 3.0 x

TC + 43

96.0

–

HREQ in deassertion to last SCK sampling

edge (HREQ in set-up time) (CPHA = 1)

Master

–

First SCK edge to HREQ in not asserted

(HREQ in hold time)

Master

–

HREQ assertion width

Master

–

3.0 x TC

–

Notes:

VCORE_VDD = 1.0± 0.10 V; TJ = -40°C to 125°C; CL = 50 pF.

Periodically sampled, not 100% tested.

All times assume noise free inputs.

All times assume internal clock frequency of 200 MHz.

SHI_1 specs match those of SHI.

Table 11. Serial Host Interface SPI Protocol Timing Parameters (Continued)

No.

Characteristics1,3,4

Mode

Filter Mode

Expression

Min

Max

Unit

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