DSP56721 datasheet(19/54 Pages) FREESCALE

19 / 54 page

SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

SS assertion to first SCK edge

CPHA = 0

Slave

Bypassed

3.5 x

TC+15

32.5

–

Very Narrow

3.5 x

TC+5

22.5

–

Narrow

–

Wide

–

CPHA = 1

Slave

Bypassed

–

Very Narrow

–

Narrow

–

Wide

–

Last SCK edge to SS not asserted

Slave

Bypassed

–

Very Narrow

–

Narrow

–

100

–

Wide

–

200

–

Data input valid to SCK edge (data input

set-up time)

Master

/Slave

Bypassed

–

Very Narrow

–

Narrow

–

Wide

–

SCK last sampling edge to data input not

valid

Master

/Slave

Bypassed

2 x TC + 10

–

Very Narrow

2 x TC + 30

–

Narrow

2 x TC + 60

–

Wide

–

100.0

–

SS assertion to data out active

Slave

–

SS deassertion to data high impedance2

Slave

–

SCK edge to data out valid

(data out delay time)

Master

/Slave

Bypassed

–

46.2

Very Narrow

–

270

Narrow

–

376

Wide

–

521

SCK edge to data out not valid

(data out hold time)

Master

/Slave

Bypassed

–

11.67

–

Very Narrow

–

Narrow

–

Wide

–

105

–

SS assertion to data out valid

(CPHA = 0)

Slave

–

14.0

Table 11. Serial Host Interface SPI Protocol Timing Parameters (Continued)

No.

Characteristics1,3,4

Mode

Filter Mode

Expression

Min

Max

Unit

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