LM10504 datasheet(24/42 Pages) TI2

24 / 42 page

LM10504

SNVS739F – DECEMBER 2011 – REVISED OCTOBER 2016

www.ti.com

Product Folder Links: LM10504

Submit Documentation Feedback

Table 1. Registers Configurable Through SPI Interface (continued)

ADDR

REG NAME

BIT

R/W

DEFAULT

DESCRIPTION

NOTES

0x08

Buck 2 voltage

—

See Table 2

Reset default:

—

Vselect_B2 = 1

→ 0x26 (3 V)

R/W

Buck 2 Voltage Code[5]

Vselect_B2 = 0

→ 0x0E (1.8 V)

R/W

Buck 2 Voltage Code[4]

R/W

Buck 2 Voltage Code[3]

Range: 1.1 V to 3.6 V

R/W

Buck 2 Voltage Code[2]

R/W

Buck 2 Voltage Code[1]

R/W

Buck 2 Voltage Code[0]

0x09

DevSLP mode

for Buck 3

R/W

See Table 3

Reset default:

Buck 3 Voltage Code[6]

Vselect_B3 = 1

→ 0x53 (1.115 V)

Buck 3 Voltage Code[5]

Vselect_B3 = 0

→ 0x0E (0.93 V)

Buck 3 Voltage Code[4]

Buck 3 Voltage Code[3]

Buck 3 Voltage Code[2]

Buck 3 Voltage Code[1]

Buck 3 Voltage Code[0]

0x0A

Buck control

BK3EN

Reads Buck 3 enable status

—

R/W

BK1FPWM

Buck 1 forced PWM mode when high

R/W

BK2FPWM

Buck 2 forced PWM mode when high

R/W

BK3FPWM

Buck 3 forced PWM mode when high

R/W

BK1EN

Enables Buck 1 0-disabled, 1-enabled

R/W

BK2EN

Enables Buck 2 0-disabled, 1-enabled

0x0B

Comparator

control

(see Table 4)

R/W

Comp_hyst[0]

Doubles Comparator hysteresis

R/W

Comp_thres[5]

Programmable range of 2 V to 4 V, step size

= 31.75 mV

R/W

Comp_thres[4]

Comparator Threshold reset default: 0x19

R/W

Comp_thres[3]

R/W

Comp_thres[2]

Comp_hyst = 1

→ min 80 mV hysteresis

R/W

Comp_thres[1]

Comp_hyst = 0

→ min 40 mV hysteresis

R/W

Comp_thres[0]

R/W

COMPEN

Comparator enable

0x0C

Interrupt enable

—

R/W

LDO OK

R/W

Buck 3 OK

R/W

Buck 2 OK

R/W

Buck 1 OK

R/W

Comparator

Interrupt comp event

LM10504 Datasheet(PDF) 24 Page - Texas Instruments

LM10504 Datasheet(HTML) 24 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL