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LM10504

SNVS739F – DECEMBER 2011 – REVISED OCTOBER 2016

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Copyright © 2011–2016, Texas Instruments Incorporated

(1)

All limits are ensured by design, test, or statistical analysis. All electrical characteristics having room-temperature limits are tested during

production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature

variations and applying statistical process control.

(2)

Capacitors: Low-ESR surface-mount ceramic capacitors (MLCCs) are used in setting electrical characteristics.

(3)

Specification ensured by design. Not tested during production.

6.5 Electrical Characteristics – General

TJ = 25°C and VIN = 5 V where VIN = VIN_B1 = VIN_B2 = VIN_B3 (unless otherwise noted)

(1) (2)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IQ(DEVSLP)

Quiescent supply current

DevSLP = HIGH,

no load

TJ = 25°C

100

µA

–30°C

≤ TJ ≤ 85°C

200

UNDERVOLTAGE OR OVERVOLTAGE LOCKOUT

VUVLO_RISING

Undervoltage lockout, rising

TJ = 25°C

2.9

V

–30°C

≤ TJ ≤ 85°C

2.75

3.05

VUVLO_FALLING

Undervoltage lockout, falling

TJ = 25°C

2.6

V

–30°C

≤ TJ ≤ 85°C

2.45

2.75

VOVLO_RISING

Overvoltage lockout, rising

5.64

V

VOVLO_FALLING

Overvoltage lockout, falling

5.54

V

DIGITAL INTERFACE

VIL

Logic input low

SPI_CS, SPI_DI, SPI_CLK, RESET,

DevSLP, –30°C

≤ TJ ≤ 85°C

0.7 × VIN_IO

0.3 × VIN_IO

V

VIH

Logic input high

SPI_CS, SPI_DI, SPI_CLK, RESET,

DevSLP, –30°C

≤ TJ ≤ 85°C

VIL

Logic input low

Vselect_B2, Vselect_B3,

–30°C

≤ TJ ≤ 85°C

0.7 × VIN

0.3 × VIN

V

VIH

Logic input high

Vselect_B2, Vselect_B3,

–30°C

≤ TJ ≤ 85°C

VOL

Logic output low

SPI_DO, –30°C

≤ TJ ≤ 85°C

0.8 × VIN_IO

0.2 × VIN_IO

V

VOH

Logic output high

SPI_DO, –30°C

≤ TJ ≤ 85°C

IIL

Input current, pin driven low

SPI_CS, SPI_DI, SPI_CLK,

Vselect_B2, DevSLP

–2

µA

Vselect_B3, RESET

–5

IIH

Input current, pin driven high

SPI_CS, SPI_DI, SPI_CLK,

Vselect_B3, RESET

2

µA

Vselect_B2, DevSLP

5

fSPI_MAX

SPI max frequency

–30°C

≤ TJ ≤ 85°C

10

MHz

tRESET

Minimum pulse width(3)

–30°C

≤ TJ ≤ 85°C

2

µs

tDEVSLP