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LM10504 Datasheet(PDF) 4 Page - Texas Instruments |
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LM10504 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 42 page ![]() 4 LM10504 SNVS739F – DECEMBER 2011 – REVISED OCTOBER 2016 www.ti.com Product Folder Links: LM10504 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NO. NAME B3 GND G Connect to system ground. C1 SPI_CLK I SPI interface: Serial clock input. C7 VCOMP I Analog input for comparator. D1 SPI_DI I SPI interface: Serial data input. D7 GND G Connect to system ground; decouple closely to A3. E1 SPI_DO O SPI interface: Serial data output. E7 DevSLP I Digital input control signal for entering device sleep mode. This is an active high pin with an internal pulldown resistor. Lowers core ASIC voltage and turns off the FLASH and I/O bucks. F1 SPI_CS I SPI interface: Chip select. F2, G2 SW_B2 P Buck switcher regulator 2: Power switching node, connect to inductor. F3 FB_B2 I Buck switcher regulator 2: Voltage output feedback. F4 Vselect_B3 I Digital input start-up control signal to change predefined output voltage of buck 3, internally pulled up as a default. F5 FB_B3 I Buck switcher regulator 3: Voltage output feedback. F6, G6 SW_B3 P Buck switcher regulator 3: Power switching node, connect to inductor. F7 RESET I Digital input control signal to abort SPI transactions; resets the PMIC to default voltages. This is an active low pin with an internal pullup. G1 GND_B2 P Buck switcher regulator 2: Power ground for buck regulator. G3 VIN_B2 P Buck switcher regulator 2: Power supply voltage input for power stage PFET, if buck 2 is not used, tie to ground to reduce leakage. G4 Vselect_B2 I Digital input start-up control signal to change predefined output voltage of buck 2, internally pulled down as a default. G5 VIN_B3 P Buck switcher regulator 3: Power supply voltage input for power stage PFET. G7 GND_B3 P Buck switcher regulator 3: Power ground for buck regulator. |
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