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TAS3202 Datasheet(PDF) 33 Page - Texas Instruments |
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TAS3202 Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 69 page ![]() CLIP DATA RAM 1022 × 48 COEF RAM 1022 × 28 PREG3 LR (PREG2) Barrel Shift, NEG, ABS, or THRU MR (PREG3) Micro Mem IF To Output SAP DI ( (3 lsbs) ) EREG3 ACC L (CREG) B (BREG) MD (AREG) MC (RREG) 32 48 76 76 48 48 76 48 48 48 48 48 48 76 28 28 48 28 2 48 28 28 48 28 48 76 48 48 28 48 28 28 48 48 28 48 48 Multiply Legend Register Output Register File (DO1 – DO8) (DREG1 – DREG8) ADD Delay RAM 5.8K × 24 DLYO (EREG1) 48 28 Operand A Operand B 76 “ZERO” VOL (5 lsbs) (EREG4) LFS (LFSR) 48 28 28-bit data 48 48-bit data 76 76-bit data BR (PREG1) 32 32-bit data LOG, ALOG, NEG, ABS, or THRU DLYI (DREG9) 48 TAS3202 www.ti.com SLES208B – JUNE 2009 – REVISED MARCH 2011 Figure 7-1. DSP Core Block Diagram Copyright © 2009–2011, Texas Instruments Incorporated Digital Audio Processor (DAP) Arithmetic Unit 33 Submit Documentation Feedback Product Folder Link(s): TAS3202 |
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