TAS3202 datasheet(9/69 Pages) TI2

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TAS3202

www.ti.com

SLES208B – JUNE 2009 – REVISED MARCH 2011

TERMINAL

INPUT/

PULLUP/

DESCRIPTION

OUTPUT(1)

PULLDOWN(2)

NAME

NO.

The frequency for this clock is 6.144 MHz/(n+1), where n is

MCLK_OUT2

Digital output

programable in the range 0 to 255. Default value is 1.024 MHz. This

output is valid even when reset is LOW.

The frequency for this clock is 512 kHz/(n+1) where n is programmable

MCLK_OUT3

Digital output

in the range 0 to 255. Default value is 512 kHz. This output is valid

even when reset is LOW.

This pin can be programmed by the application firmware to mute the

MUTE

Digital input

Pulldown

TAS3202. It has no default functionality

20–23,

No connect

29–32

This pin can be programmed by the application firmware to power down

PDN

Digital input

the TAS3202. Default operation is to stop the DSP.

RESERVED

N/A

Pulldown

Connect to ground.

System reset input, active low. A system reset is generated by applying

RESET

Digital input

Pullup

a logic LOW to this terminal.

Requires a 22-k

Ω (1%) external resistor to ground to set analog

REXT

Analog output

currents. Trace capacitance must be kept low.

SCLK_IN

Digital input

Serial data input bit clock for I2S interface

SCLK_OUT

Digital output

Serial data output bit clock for I2S interface

SDIN1/GPIO3

Digital I/O

Pullup

Serial data input 1 for I2S interface or programmable for GPIO #3

SDIN2/GPIO4

Digital I/O

Pullup

Serial data input 2 for I2S interface or programmable for GPIO #4

SDOUT1

Digital output

Serial data output 1 for I2S interface

SDOUT2

Digital output

Serial data output 2 for I2S interface

Analog mid supply reference. This pin must be decoupled with a 0.1-

μF

VMID

Analog output

low-ESR capacitor and an external 10-

μF filter cap.(4)

Voltage reference for analog supply. A pinout of the internally regulated

1.8-V power. A 0.1-

μF low ESR capacitor and a 4.7-μF filter capacitor

VR_ANA

Power

must be connected between this terminal and AVSS_PLL. This terminal

must not be used to power external devices.(4)

Voltage reference for digital supply. A pinout of the internally regulated

1.8-V power. A 0.1-

μF low ESR capacitor and a 4.7-μF filter capacitor

VR_DIG

Power

must be connected between this terminal and DVSS. This terminal

must not be used to power external devices.(4)

Voltage reference for DPLL supply. A pinout of internally regulated

1.8-V power supply. A 0.1-

μF low-ESR capacitor and a 4.7-μF filter

VR_PLL

Power

capacitor must be connected between this terminal and DVSS. This

terminal must not be used to power external devices.(4)

Bandgap output. A 0.1-

μF low ESR capacitor should be connected

VREF

Analog output

between this terminal and AVSS_PLL. This terminal must not be used

to power external devices.(4)

Voltage regulator enable. When enabled LOW, this input causes the

VREG_EN

Digital input

power-supply regulators to be enabled.

XTAL_IN

Digital input

Crystal input. A 24.576-MHz (512Fs) crystal should be used.

XTAL_OUT

Digital output

Crystal output

(4)

If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling

capacitors of equal value provide an extended high-frequency supply decoupling.

Physical Characteristics

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