TAS3202 datasheet(5/69 Pages) TI2

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DPLL

×5.5

÷4

135-MHz DCLK

Microprocessor Clock

MCLK_OUT

MCLK_OUT2

MCLK_OUT3

Programmable

Divider

÷2

÷64

÷2

Programmable

Divider

Master/

Slave

LRCLK_OUT

SCLK_OUT

SDOUT

To DAP

Parallel

Data

SDIN

From DAP

Parallel

Data

LRCLK

Re-Creation

Serial

Audio Port

Receiver

Serial

Audio Port

Transmitter

256Fs

128Fs

64Fs

512Fs

Crystal

MCLKI

24.576 MHz

Oscillator

24.576 MHz

TAS3202

www.ti.com

SLES208B – JUNE 2009 – REVISED MARCH 2011

2.5

Clocks, Digital Phase-Locked Loop (PLL), and Serial Data Interface

These modules provide the timing and serial data interface for the TAS3202. The clocking system for the

device is illustrated in Figure 2-1. The TAS3202 can be either clock master or clock slave depending on

the configuration. However, clock master mode is the primary mode of operation.

Figure 2-1. Clock Generation

DISCLAIMER: Analog performance is not ensured in slave mode, as the analog performance depends

upon the quality of the MCLK_IN. The TAS3202 is not robust with respect to MCLK_IN errors (glitches,

etc.); if the MCLK_IN frequency changes under operation, the device must be reset.

I2C clock master operation:

•

External 512Fs crystal oscillator is used to generate all internal clocks plus all clocks for external

asynchronous sampling rate converter (ASRC) output (if external ASRC is present).

•

LRCLK_OUT is fixed at 48 kHz (Fs).

•

SCLK_OUT is fixed at 64Fs.

•

MCLK_OUT is fixed at 256Fs. In master mode, the external ASRC converts incoming serial audio data

to 48-kHz sample rate synchronous to the internally generated serial audio data clocks.

•

In master mode, all clocks generated for the TAS3202 are derived from the 24.576-MHz crystal. The

internal oscillator drives the crystal and generates the main clock to digital PLL (DPLL), master clock

outputs, 256Fs clock to the ADC, and 128Fs clock to the DAC. The DPLL generates internal clocks for

the DAP and the 8051 microprocessor.

Functional Description

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