TAS3202 datasheet(6/69 Pages) TI2

6 / 69 page

TAS3202

SLES208B – JUNE 2009 – REVISED MARCH 2011

www.ti.com

I2S clock slave operation:

•

MCLK_IN (512Fs), SCLK_IN (64Fs), and LRCLK_IN (Fs) are supplied externally. Clock generation is

similar to the master mode with the exception of the ADC and the DAC blocks. MCLK_IN signal is

divided down and sent directly to the ADC and the DAC blocks. Therefore, audio performance

depends on the MCLK_IN signal.

•

DSP, MCU, and I2C clocks are still derived from external crystal oscillator.

•

MCLK_OUT, SCLK_OUT, and LRCLK_OUT are passed through from clock inputs (MCLK_IN,

SCLK_IN, and LRCLK_IN).

•

Internal analog clocks for ADC and DACs are derived from external MCLK_IN input, so analog

performance depends on MCLK_IN quality (i.e., jitter, phase noise, etc.). Degradation in analog

performance is to be expected.

•

Sample rate change/clock change

–

Sample rate change on the fly should be handled by the customer system controller. The TAS3202

device does not include any internal clock error or click/pop detection/management.

–

Sample rate dependent DAP filter coefficients must be uploaded by customer system controller on

changing sample rate.

In I2S clock slave mode, all incoming serial audio data must be synchronous to an incoming LRCLK_IN of

44.1 kHz or 48 kHz.

2.6

2C Control Interface

The TAS3202 has an I2C slave-only interface (SDA1 and SCL1) for receiving commands and providing

status to the system controller, and a separate master I2C interface (SDA2 and SCL2) to download

programs and data from external memory, such as an EEPROM. See Section 6 for more information. I2C

interface is not 5-V tolerant.

2.7

8051 Microcontroller

The 8051 microcontroller receives and distributes I2C write data. It retrieves and outputs data as

requested from the I2C bus controller. It performs most processing tasks requiring multi-frame processing

cycles. The microprocessor has its own data RAM for storing intermediate values and queuing I2C

commands, a fixed boot program ROM, and a programmable RAM. The microprocessor's boot program

cannot be altered. The microcontroller has specialized hardware for an I2C master and slave interface

operation, volume updates, and a programmable interval-timer interrupt.

2.8

Audio Digital Signal Processor (DSP) Core

The audio DSP core arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit

and data and coefficient memory blocks. The audio processing structure, which can include mixers,

multiplexers, volume, bass and treble, equalizers, dynamic range compression, or third-party algorithms, is

running in the DAP. The 8051 microcontroller has access to digital audio processor (DAP) resources such

as coefficient RAM and is able to support the DAP with certain tasks; for example, a volume ramp. The

primary blocks of the audio DSP core are:

•

48-bit data path with 76-bit accumulator

•

DSP controller

•

Memory interface

•

Coefficient RAM (1K×28)

•

Data RAM – 24-bit upper memory (1K×24), 48-bit lower memory (768×48)

•

Program RAM (3K×55)

Functional Description

Submit Documentation Feedback

Product Folder Link(s): TAS3202

TAS3202 Datasheet(PDF) 6 Page - Texas Instruments

TAS3202 Datasheet(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Datasheet Download

Link URL