TAS3202 datasheet(10/69 Pages) TI2

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TAS3202

SLES208B – JUNE 2009 – REVISED MARCH 2011

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3.3

Reset (RESET) Power-Up Sequence

The RESET pin is an asynchronous control signal that restores all TAS3202 components to the default

configuration. When a reset occurs, the audio DSP core is put into an idle state and the 8051 starts

initialization. A valid XTAL_IN must be present when clearing the RESET pin to initiate a device reset. A

reset can be initiated by applying a logic 0 on RESET.

As long as RESET is held LOW, the device is in the reset state. During reset, all I2C and serial data bus

operations are ignored. The I2C interface SCL and SDA lines go into a high-impedance state and remain

in that state until device initialization has completed.

The rising edge of the reset pulse begins the initialization housekeeping functions of clearing memory and

setting the default register values. Once these are complete, the TAS3202 enables its master I2C interface

and disables its slave I2C interface.

Using the master interface, the TAS3202 automatically tests to see if an external I2C EEPROM is at

address 1010x. The value x can be chip selects, other information, or don't care, depending on the

EEPROM selected.

If a memory is present and it contains the correct header information and one or more blocks of

program/memory data, the TAS3202 begins to load the program, coefficient and/or data memories from

the external EEPROM. If an external EEPROM is present, the download is considered complete when an

end-of-program header is read by the TAS3202. At this point, the TAS3202 disables the master I2C

interface, enables the slave I2C interface, and starts normal operation. After a successful download, the

micro program counter is reset, and the downloaded micro and DAP application firmware controls

execution.

If no external EEPROM is present or if an error occurs during the EEPROM read, TAS3202 disables the

master I2C interface, enables the slave I2C interface, and proceeds to boot the device according to the

ROM. In this default ROM configuration, the TAS3202 streams audio from input to output if the GPIO1 pin

is asserted logic low on reset; if the GPIO1 pin is asserted logic high, the ADC and the DAC are muted.

NOTE

The master and slave I

2C interfaces do not operate simultaneously.

3.4

Voltage Regulator Enable (VREG_EN)

Setting the VREG_EN high shuts down all voltage regulators in the device. Internal register settings are

lost in this power-down mode. A full power-up/reset/program-load sequence must be completed before the

device is operational.

3.5

Power-On Reset (RESET)

On power up, it is recommended that the TAS3202 RESET be held low until DVDD has reached 3.3 V.

This can be done by programming the system controller or by using an external RC delay circuit. The

1-k

Ω and 1-μF values provide a delay of approximately 200 μs. The values of R and C can be adjusted to

provide other delay values as necessary.

Physical Characteristics

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