SID1182K datasheet(7/24 Pages) POWERINT

7 / 24 page

Rev. H 09/19

SID11x2K

To avoid parasitic power-switch-conduction during system power-on,

the gate is connected to COM through 6.8 kW resistor.

Figure 13 shows how switch desaturation can be measured using

resistors R

VCE2 – RVCE11. In this example all the resistors have a value

of 100 kW and 1206 size. The total resistance is 1 MW. The resistors

should be chosen to limit current to between 0.6 mA to 0.8 mA at

maximum DC-link voltage. The sum of R

VCE2 – RVCE11 should be

approximately 1 MW for 1200 V semiconductors and 500 kW for 600 V

semiconductors. In each case the resistor string must provide

sufficient creepage and clearance distances between collector of the

semiconductor and SCALE-iDriver. The low leakage diode D

CL keeps

the short-circuit duration constant over a wide DC-link voltage range.

Response time is set up through R

VCE and CRES (typically 120 kW and

33 pF respectively for 1200 V semiconductors). If short-circuit

detection proves to be too sensitive, the C

RES value can be increased.

The maximum short-circuit duration must be limited to the maximum

value given in the semiconductor data sheet.

Figure 14 illustrates how diodes D

VCE1 and DVCE2 may be used to

measure switch desaturation. For insulation, two diodes in SMD

packages are used (STTH212U for example). R

RES connected to VISO

guarantees current flow through the diodes when the semiconductor

is in the on-state. When the switch desaturates, C

RES starts to be

charged through R

RES. In this configuration the response time is

controlled by R

RES and CRES. In this application example CRES = 33 pF

and R

RES = 62 kW; if desaturation is too sensitive or the short-circuit

duration too long, both C

RES and RRES can be adjusted.

Figure 15 shows the recommended PCB layout and corresponds to

the schematic in Figure 13. The PCB is a two layer design. It is

important to ensure that PCB traces do not cover the area below the

desaturation resistors or diodes D

VCE1 and DVCE2. This is a critical

design requirement to avoid coupling capacitance with the SCALE-

iDriver’s VCE pin and isolation issues within the PCB.

Gate resistors are located physically close to the power semiconductor

switch. As these components can get hot, it is recommended that

they are placed away from the SCALE-iDriver.

Power Dissipation and IC Junction

Temperature Estimation

First calculation in designing the power semiconductor switch gate

driver stage is to calculate the required gate power - P

DRV. The power

is calculated based on equation 1:

DRV

GATES

TOT

(1)

where,

GATE – Controlled power semiconductor switch gate charge (derived

for the particular gate potential range defined by V

TOT). See semicon-

ductor manufacturer data sheet.

S – Switching frequency which is same as applied to the IN pin of

SCALE-iDriver.

TOT – SCALE-iDriver secondary-side supply voltage.

In addition to P

DRV, PP (primary-side IC power dissipation) and PSNL

(secondary-side IC power dissipation without capacitive load) must be

considered. Both are ambient temperature and switching frequency

dependent (see typical performance characteristics).

VCCVCC

(2)

TOTVISO

SNL

(3)

During IC operation, the P

DRV power is shared between turn-on (RGH),

turn-off (R

GL) external gate resistors and internal driver resistances

GHI and RGLI. For junction temperature estimation purposes, the

dissipated power under load (P

OL) inside the IC can be calculated

accordingly to equation 4:

GATE

TOT

GHIGH

GHI

GHLGL

GHL

(4)

GH and RGL represent sum of external (RGON, RGOFF) and power

semiconductor internal gate resistance (R

GINT):

GONGINT

GOFF

GINT

Total IC power dissipation (P

DIS) is estimated as sum of equations 2, 3

and 4:

DISOL

PSNL

(5)

The operating junction temperature (T

J) for given ambient tempera-

ture (T

A) can be estimated according to equation 6:

JJADIS

(6)

Example

An example is given below,

S = 20 kHz, TA = 85 °C, VTOT = 25 V, VVCC = 5 V.

GATE = 2.5 µC (the gate charge value here should correspond to

selected V

TOT), RGINT = 2.5 W, RGON = RGOFF = 1.8 W.

DRV = 2.5 µC × 20 kHz × 25 V = 1.25 W, according to equation 1.

P = 5 V × 13.5 mA = 67 mW, according to equation 2 (see Figure 18).

SNL = 25 V × 7.5 mA = 185 mW, according to equation 3 (see Figure 20).

The dissipated power under load is:

P0 52 5C

20 kHz25V

1454 3

145

≅

according to equation 4.

GHI = 1.45 W as maximum data sheet value.

GHL = 1.2 W as maximum data sheet value.

GH = RGL = 1.8 W + 2.5 W = 4.3 W.

DIS = 67 mW + 185 mW + 300 mW = 552 mW according to equation 5.

J = 67 °C/W × 552 mW + 85 °C = 122 °C according to equation 6.

Estimated junction temperature for this design would be approximately

122 °C and is lower than the recommended maximum value. As the

gate charge is not adjusted to selected V

TOT and internal IC resistor

values are maximum values, it is understood that the example

represents worst-case conditions.

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