Rev. H 09/19

16

SID11x2K

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Figure 16. Thermal Derating Curve Showing Dependence of Limited Dissipated Power on Case Temperature

(DIN V VDE V 0884-10).

Continuous device operating is allowed until T

J and/or TC of 125 °C are reached. Thermal stress beyond those values but below thermal derating

curve may lead to permanent functional product damage. Operating beyond thermal SR derating curve may affect product reliability.

NOTES:

1. V

VCC = 5 V, VTOT = 25 V; GH and GL pins are shorted together. RG = 4 W, No CG; VCC pin is connected to the SO pin through a 2 kW resistor.

The VGXX pin is connected to the GH pin through a 10 nF capacitor. Typical values are defined at T

A = 25 °C; fS = 20 kHz, Duty Cycle =

50%. Positive currents are assumed to be flowing into pins.

2. Pulse width ≤ 10 µs, duty cycle ≤ 1%. The maximum value is controlled by the ASIC to a safe level. There is no need to limit the current by

the application. The internal peak power is safely controlled for R

G ≥ 0 and power semiconductor module input gate capacitance CIES ≤ 47 nF.

3. During very slow V

VCC power-up and power-down related to VTOT, VVCC and VVEE respectively, several SO fault pulses may be generated.

4. SO pin connected to GND as long as V

VCC stays below minimum value. No signal transferred from primary to secondary-side.

5. V

IN potential changes from 0 V to 5 V within 10 ns. Delay is measured from 50% voltage increase on IN pin to 10% voltage increase

on GH pin.

6. V

IN potential changes from 5 V to 0 V within 10 ns. Delay is measured from 50% voltage decrease on IN pin to 10% voltage decrease

on GL pin.

7. Measured from 10% to 90% of V

GE (CG simulates semiconductor gate capacitance). The VGE is measured across CG.

8. Measured from 90% to 10% of V

GE (CG simulates semiconductor gate capacitance). The VGE is measured across CG.

9. ASSD function limits G-E voltage of controlled semiconductor in specified time. Conditions: C

G = 10 nF, VTOT = VVISO = 15 V,

V

VEE = 0 V (VEE shorted to COM).

10. The amount of time needed to transfer fault event (UVLO or DESAT) from secondary-side to SO pin.

11. The amount of time after primary and secondary-side supply voltages (V

VCC and VTOT) reach minimal required level for driver proper

operation. No signal is transferred from primary to secondary-side during that time, and no fault condition will be transferred from the

secondary-side to the primary-side.

12. Guaranteed by design.

13. Positive current is flowing out of the pin.

14. Safety distances are application dependent and the creepage and clearance requirements should follow specific equipment isolation

standards of an application. Board design should ensure that the soldering pads of an IC maintain required safety relevant distances.

15. Measured accordingly to IEC 61000-4-8 (f

S = 50 Hz, and 60 Hz) and IEC 61000-4-9.

16. All pins on each side of the barrier tied together creating a two-terminal device.

0

20

40

60

80

100

120

140

160

TC (°C)

2.0

1.8

1.4

1.6

1.2

0.6

0.8

1.0

0.4

0.0

0.2