AD7148 datasheet(39/56 Pages) AD

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AD7148

Rev. 0 | Page 39 of 56

Table 23. STAGEx_HIGH_INT_EN Register

Address

Data Bit

Default

Value

Type

Mnemonic

Description

0x006

[0]

R/W

STAGE0_HIGH_INT_EN

STAGE0 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[1]

R/W

STAGE1_HIGH_INT_EN

STAGE1 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE1 high threshold is exceeded

[2]

R/W

STAGE2_HIGH_INT_EN

STAGE2 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE2 high threshold is exceeded

[3]

R/W

STAGE3_HIGH_INT_EN

STAGE3 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE3 high threshold is exceeded

[4]

R/W

STAGE4_HIGH_INT_EN

STAGE4 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE4 high threshold is exceeded

[5]

R/W

STAGE5_HIGH_INT_EN

STAGE5 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE5 high threshold is exceeded

[6]

R/W

STAGE6_HIGH_INT_EN

STAGE6 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE6 high threshold is exceeded

[7]

R/W

STAGE7_HIGH_INT_EN

STAGE7 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE7 high threshold is exceeded

[15:8]

Unused

Set unused register bits to 0

AD7148 Datasheet(PDF) 39 Page - Analog Devices

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