AD7148 datasheet(41/56 Pages) AD

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AD7148

Rev. 0 | Page 41 of 56

Table 26. STAGEx_HIGH_LIMIT_INT Register1

Address

Data

Bit

Default

Value

Type

Mnemonic

Description

0x009

[0]

STAGE0_HIGH_LIMIT_INT

STAGE0 CDC conversion high limit interrupt result

1 = indicates STAGE0_HIGH_THRESHOLD value exceeded

[1]

STAGE1_HIGH_LIMIT_INT

STAGE1 CDC conversion high limit interrupt result

1 = indicates STAGE1_HIGH_THRESHOLD value exceeded

[2]

STAGE2_HIGH_LIMIT_INT

Stage2 CDC conversion high limit interrupt result

1 = indicates STAGE2_HIGH_THRESHOLD value exceeded

[3]

STAGE3_HIGH_LIMIT_INT

STAGE3 CDC conversion high limit interrupt result

1 = indicates STAGE3_HIGH_THRESHOLD value exceeded

[4]

STAGE4_HIGH_LIMIT_INT

STAGE4 CDC conversion high limit interrupt result

1 = indicates STAGE4_HIGH_THRESHOLD value exceeded

[5]

STAGE5_HIGH_LIMIT_INT

STAGE5 CDC conversion high limit interrupt result

1 = indicates STAGE5_HIGH_THRESHOLD value exceeded

[6]

STAGE6_HIGH_LIMIT_INT

STAGE6 CDC conversion high limit interrupt result

1 = indicates STAGE6_HIGH_THRESHOLD value exceeded

[7]

STAGE7_HIGH_LIMIT_INT

STAGE7 CDC conversion high limit interrupt result

1 = indicates STAGE7_HIGH_THRESHOLD value exceeded

[15:8]

Unused

Set unused register bits to 0

1 Registers self-clear to 0 after readback, provided that the limits are not exceeded.

Table 27. STAGEx_COMPLETE_INT_STATUS Register1

Address

Data

Bit

Default

Value

Type

Mnemonic

Description

0x00A

[0]

STAGE0_COMPLETE_INT_STATUS

STAGE0 conversion complete register interrupt status

1 = indicates STAGE0 conversion completed

[1]

STAGE1_COMPLETE_INT_STATUS

STAGE1 conversion complete register interrupt status

1 = indicates STAGE1 conversion completed

[2]

STAGE2_COMPLETE_INT_STATUS

STAGE2 conversion complete register interrupt status

1 = indicates STAGE2 conversion completed

[3]

STAGE3_COMPLETE_INT_STATUS

STAGE3 conversion complete register interrupt status

1 = indicates STAGE3 conversion completed

[4]

STAGE4_COMPLETE_INT_STATUS

STAGE4 conversion complete register interrupt status

1 = indicates STAGE4 conversion completed

[5]

STAGE5_COMPLETE_INT_STATUS

STAGE5 conversion complete register interrupt status

1 = indicates STAGE5 conversion completed

[6]

STAGE6_COMPLETE_INT_STATUS

STAGE6 conversion complete register interrupt status

1 = indicates STAGE6 conversion completed

[7]

STAGE7_COMPLETE_INT_STATUS

STAGE7 conversion complete register interrupt status

1 = indicates STAGE7 conversion completed

[15:8]

Unused

Set unused register bits to 0

1 Registers self-clear to 0 after readback, provided that the limits are not exceeded.

AD7148 Datasheet(PDF) 41 Page - Analog Devices

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